Gray codes are a binary numeral system where two successive values differ in only one bit. They were invented by Emile Baudot in the late 1800s for use in telegraph systems. Forming a Gray code involves starting with all zeros and changing the least significant bit to form each new code word. Implementing a Gray code sequence in an FPGA using a state machine can avoid output glitches, but different synthesis tools may or may not correctly interpret the VHDL to generate a true Gray code sequence rather than a standard binary encoding.

1. Gray Codes
Gray Codes 1

2. Gray Codes
“This is rookie stuff, so I can duck
out of this module, get some cookies,
and come back later, right?”
Gray Codes 2

3. History of the Gray Code
• Invented by Emile Baudot (1845-1903)
• Originally called a “cyclic-permuted” code
• Telegraph - 5 bit codes
– Bits stored on a code wheel in the receiver
– Wheel connected to the printing disk
– Matched pattern on wheel and received pattern and
then actuated head to print.
• Exhibited at Universal Exposition, Paris (1878)
Gray Codes 3

4. Forming a Gray Code
• Start with all 0's
• Change the least significant bit that forms a
new code word
a b c d e
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 0 1 0 0 0 1 0 0 0 1 0
0 1 1 0 0 1 1 0
0 1 1 1
Gray Codes 4

5. Binary Reflected Gray Code
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 1
2 1 1 2 0 0 1 1
3 1 0 3 0 0 1 0
4 0 1 1 0
5 0 1 1 1
6 0 1 0 1
0 0 0 0
7 0 1 0 0
1 0 0 1
8 1 1 0 0
2 0 1 1
9 1 1 0 1
3 0 1 0
10 1 1 1 1
4 1 1 0
11 1 1 1 0
5 1 1 1
12 1 0 1 0
6 1 0 1
13 1 0 1 1
7 1 0 0
14 1 0 0 1
15 1 0 0 0
Gray Codes 5

6. Reflected Gray and Binary Codes
Binary Gray
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Gray Codes 6

7. Why Gray Codes?
• Single output changes at a time
– Asynchronous sampling
– Permits asynchronous combinational circuits to
operate in fundamental mode
– Potential for power savings
• Multiphase, multifrequency clock generator
Gray Codes 7

8. Effects of Errors
• Lockup States
– None if all states are used
– Can’t use all states for one-hot
• Magnitude of Error
– Reduced to one code word
– Binary can jump 1/2 scale
Gray Codes 8

9. A Parallel Binary to Gray
Converter
MSB B3 G3
G2
B2
G1
B1
G0
LSB B0
Very fast conversion
Gray Codes 9

10. Binary Counter + Gray Code
Converter: Glitch Free?
Binary
Binary to
Counter Gray
Converter
CLK
Gray Codes 10

11. Binary Counter + Converter
Glitch Free Decoding?
Discuss
Binary
Binary to
Counter Gray
Converter
CLK
Gray Codes 11

12. A Parallel Gray to Binary
Converter
MSB B3 G3
G2
B2
G1
B1
G0
LSB B0
Very slow conversion
Gray Codes 12

13. VHDL Code for a 4-Bit Gray
Code Sequencer (1)
Package Gray_Types Is
Type States Is ( s0, s1, s2, s3,
s4, s5, s6, s7,
s8, s9, s10, s11,
s12, s13, s14, s15 );
End Package Gray_Types;
Gray Codes 13

14. VHDL Code for a 4-Bit Gray
Code Sequencer (2)
Architecture RTL of Gray_Code Is
Library IEEE;
Attribute syn_netlist_hierarchy of RTL : architecture is false;
Use IEEE.Std_Logic_1164.all;
Library Work;
Signal IQ : States;
Use Work.Gray_Types.All;
Attribute syn_encoding of IQ : signal is "gray";
Library synplify;
Begin
Use synplify.attributes.all;
GC: Process ( Clock, Reset_N )
Begin
Entity Gray_Code Is
If ( Reset_N = '0' )
Then IQ <= s0;
Port ( Clock : In Std_Logic;
Else If Rising_Edge ( Clock )
Reset_N : In Std_Logic;
Then Case IQ Is
Q : Out States );
When s0 => IQ <= s1;
End Entity Gray_Code;
When s1 => IQ <= s2;
When s2 => IQ <= s3;
When s3 => IQ <= s4;
When s4 => IQ <= s5;
When s5 => IQ <= s6;
When s6 => IQ <= s7;
When s7 => IQ <= s8;
When s8 => IQ <= s9;
When s9 => IQ <= s10;
When s10 => IQ <= s11;
When s11 => IQ <= s12;
When s12 => IQ <= s13;
When s13 => IQ <= s14;
When s14 => IQ <= s15;
When s15 => IQ <= s0;
When Others => IQ <= s0;
End Case;
End If;
End If;
End Process GC;
Q <= IQ;
End Architecture RTL;
Gray Codes 14

15. Synplicity Output for a Gray
Code Sequencer - SX Target
E
B
A C F
D
Logic Equations:
A: ~D2 ~S10+D2 ~S00
B: D0 ~S00 ~S10+D1 S00 ~S10+D1 ~S00 S10+D0 S00 S10
C: D0 ~S00 ~S10+D1 S00 ~S10+~D0 ~S00 S10+D0 S00 S10
D: D0 ~S01+D1 ~S00 S01+D0 S00
E: ~D0 ~S00 ~S10+D0 S00 ~S10+D0 ~S00 S10+~D0 S00 S10
F: D0 ~S00 ~S10 +~D0 S00 ~S10+~D0 ~S00 S10+D0 S00 S10
Gray Codes 15

16. Synplicity Output for a Gray
Code Sequencer - SX Target
net -vsm "D:designs time = 9000.0ns Q=0000
sequencersgray_code4.vsm" time = 10000.0ns Q=1000
time = 11000.0ns Q=1100
clock clock 1 0 time = 12000.0ns Q=0100
stepsize 500ns time = 13000.0ns Q=0110
time = 14000.0ns Q=1110
vector q q_3 q_2 q_1 q_0 time = 15000.0ns Q=1010
radix bin q time = 16000.0ns Q=0010
watch q time = 17000.0ns Q=0011
time = 18000.0ns Q=1011
l reset_n time = 19000.0ns Q=1111
cycle 8 time = 20000.0ns Q=0111
time = 21000.0ns Q=0101
h reset_n time = 22000.0ns Q=1101
cycle 32 time = 23000.0ns Q=1001
time = 24000.0ns Q=0001
time = 25000.0ns Q=0000
Gray Codes 16

17. Synplicity Output for a Gray
Code Sequencer - SX Target
Continue Discussion
Gray Codes 17

18. Synplicity Output for a Gray
Code Sequencer - SX Target
Outputs are not always driven by a flip-flop
Gray Codes 18

19. Synplicity1 Synthesis Issues
• Synthesizer ignored the command to make the
state machine a Gray code and decided to make
it a one-hot machine. Had to “fiddle” with the
VHDL compiler settings for default FSM.
– Signal IQ : States;
– Attribute syn_encoding of IQ : signal is "gray";
• Output glitches!!!!!!!!
1Synplify version 5.1.5
Gray Codes 19

20. FSM Gray Codes and HDL
The Saga Continues ...
We had another engineer (HDL specialist) run the
same Gray coded FSM through his version of
Synplicity and what did he get …
… Yes, as the cynic would expect, a different
answer!
Gray Codes 20

21. FSM Gray Codes and HDL
The Saga Continues ...
Here's the key part of the output listing:
Encoding state machine work.Gray_Code(rtl)-
q_h.q[0:15]
original code -> new code
0000000000000001 -> 0000
0000000000000010 -> 0001
...
1000000000000000 -> 1000
… So far so good!
Gray Codes 21

22. FSM Gray Codes and HDL
The Saga Continues ...
But then ...
Replicating q_h.q[3], fanout 13 segments 2
Replicating q_h.q[2], fanout 13 segments 2
Replicating q_h.q[1], fanout 12 segments 2
Replicating q_h.q[0], fanout 12 segments 2
Added 0 Buffers
Added 4 Cells via replication
Resource Usage Report of Gray_Code
Sequential Cells: 8 of 1080 (1%)
dfc1b: 8
Gray Codes 22

23. FSM Gray Codes and HDL
The Saga Continues ...
Package Gray_Types Is begin
GC : process ( Clock, Reset_N )
Type States Is ( s0, s1, s2, s3, begin
s4, s5, s6, s7, if ( Reset_N = '0' )
s8, s9, s10, s11, then IQ <= s0;
s12, s13, s14, s15); else if Rising_Edge ( Clock ) then
case IQ is
End Package Gray_Types; when s0 => IQ <= s1;
when s1 => IQ <= s2;
library IEEE; when s2 => IQ <= s3;
use IEEE.Std_Logic_1164.all; when s3 => IQ <= s4;
when s4 => IQ <= s5;
library Work; when s5 => IQ <= s6;
use Work.Gray_Types.all; when s6 => IQ <= s7;
when s7 => IQ <= s8;
library synplify; when s8 => IQ <= s9;
use synplify.attributes.all; when s9 => IQ <= s10;
when s10 => IQ <= s11;
entity Gray_Code is Synplicity VHDL Compiler, version 6.2.0 when s11 => IQ <= s12;
when s12 => IQ <= s13;
port ( Clock : in std_logic; when s13 => IQ <= s14;
Reset_N : in std_logic; when s14 => IQ <= s15;
Q : out States ); when s15 => IQ <= s0;
end entity Gray_Code; when others => IQ <= s0;
end case;
architecture RTL of Gray_Code is end if;
attribute syn_netlist_hierarchy of RTL : end if;
architecture is false; end process GC;
signal IQ : States; Q <= IQ;
attribute syn_encoding of IQ : signal is "gray";
end architecture RTL;
Gray Codes 23

24. FSM Gray Codes and HDL
The Saga Continues ...
Automatic Flip-flop Replication
Gray Codes 24

25. 4-Bit Gray Code
No Enumerations or FSM Optimization (1)
library IEEE; begin
use IEEE.Std_Logic_1164.all; GC : process (Clk, Reset_N)
entity graycntr_lookup is begin
port ( Clk : in std_logic; if ( Reset_N = '0' )
Reset_N : in std_logic; then IQ <= "0000";
Q : out std_logic_vector(3 downto 0)); else if Rising_Edge ( Clk ) then
end entity graycntr_lookup; case IQ is
when "0000" => IQ <= "0001";
architecture RTL of graycntr_lookup is when "0001" => IQ <= "0011";
signal IQ : std_logic_vector(3 downto 0); when "0011" => IQ <= "0010";
when "0010" => IQ <= "0110";
when "0110" => IQ <= "0111";
when "0111" => IQ <= "0101";
when "0101" => IQ <= "0100";
when "0100" => IQ <= "1100";
when "1100" => IQ <= "1101";
when "1101" => IQ <= "1111";
• No enumerations when "1111" => IQ <= "1110";
when "1110" => IQ <= "1010";
• Synplicity VHDL Compiler, version 6.2.0 when "1010" => IQ <= "1011";
when "1011" => IQ <= "1001";
when "1001" => IQ <= "1000";
when "1000" => IQ <= "0000";
when others => IQ <= "0000";
end case;
end if;
end if;
end process GC;
Q <= IQ;
end architecture RTL;
Gray Codes 25

26. 4-Bit Gray Code
No Enumerations or FSM Optimization (1)
time = 8000.0ns RESET_N=0 Q=0000
time = 9000.0ns RESET_N=1 Q=0000 0
time = 10000.0ns RESET_N=1 Q=0001 1
time = 11000.0ns RESET_N=1 Q=0011 2
time = 12000.0ns RESET_N=1 Q=0010 3
time = 13000.0ns RESET_N=1 Q=0110 4
time = 14000.0ns RESET_N=1 Q=0111 5
time = 15000.0ns RESET_N=1 Q=0101 6
time = 16000.0ns RESET_N=1 Q=0100 7
time = 17000.0ns RESET_N=1 Q=1100 8
time = 18000.0ns RESET_N=1 Q=1101 9
time = 19000.0ns RESET_N=1 Q=1111 10
time = 20000.0ns RESET_N=1 Q=1110 11
time = 21000.0ns RESET_N=1 Q=1010 12
time = 22000.0ns RESET_N=1 Q=1011 13
time = 23000.0ns RESET_N=1 Q=1001 14
time = 24000.0ns RESET_N=1 Q=1000 15
time = 25000.0ns RESET_N=1 Q=0000 0
Gray Codes 26

27. 4-Bit Gray Code
No Enumerations or FSM Optimization (1)
Flip-flop outputs routed directly to outputs.
Gray Codes 27

28. References
• “Origins of the Binary Code,” F. G. Hearth,
Scientific American, August 1972, pp. 76-83
Gray Codes 28