The document summarizes the modeling of a magnetic tunnel junction (MTJ) using HSPICE. It describes the key components of the MTJ macro-model including electrodes, a decision-making circuit, bi-stable amplification, and a curve-fitting circuit. Simulation results show the MTJ resistance switching between 1.8kΩ and 4.5kΩ as expected. A 1T-1MTJ MRAM cell is also modeled to demonstrate read, write, and hold operations. Finally, a 2x2 MRAM array is shown to verify the design can be extended to larger arrays.

1. HSPICE Based Macro-model of
Magnetic Tunnel Junctions
Niharika S. Vranda Baweja Priya Pandey
M.Tech VLSI(1st
Year ) M.Tech VLSI(1st
Year ) M.Tech VLSI(1st
Year )
VIT University VIT University VIT University
Under The Guidance Of:
Prof. Ramakrishnan V N
VLSI Division
VIT University
Tamil Nadu, India
Abstract – Metal tunnel junctions (MTJs) are one of the
emerging trends in the memory designing that can store
the bit ‘0’ or ‘1’ depending on the resistivity of the device.
When the relative magnetic orientation of the two layers is
parallel, the device has a low resistance. When the two
layers are antiparallel, the device has a high resistance.
This work deals with the modeling of the characteristics of
MTJ sub circuit using HSPICE simulator. The sub circuit
is modeled as a two-terminal device exhibiting the electrical
characteristics of an STT-MTJ, including all the major
characteristics of an MTJ. Further The modeled MTJ is to
be connected along with an NMOS device to act as a basic
1T-1MTJ memory cell called as an MRAM cell. The
MRAM is designed to efficiently store, hold and retrieve bit
stored in it.
Keyword – Magnetic Tunnel Junction (MTJ), Spin
Transfer Torque (STT), MRAM cell
I. INTRODUCTION
Magnetic Tunnel Junctions are those devices which
have the property of magneto resistance. The relative magnetic
orientation of two ferromagnetic layers which are separated by
an insulator estimates the electrical resistance of the device. In
case of parallel relative orientation of the two magnetic layers,
the device exhibits low resistance, and in case of anti-parallel
relative orientation, it exhibits high resistance. One of the two
layers is generally fixed by anti-ferromagnetically coupling it.
The fixed layer has high coercivity and its orientation is not
changed in normal condition. The change in the magnetic
orientations of the free layer relative to the fixed layer will
determine the resistance of the device, and this can be helpful
in storing the binary data in the MTJ, which is used as a basic
storage element in the MRAM cell.
The direction of the magnetizations of the ferromagnetic
layers can be switched individually by an external magnetic
field. If the magnetizations of the two layers are in a parallel
orientation, then it is more likely that the electrons will tunnel
through the insulating film compared to if they are in the
antiparallel orientation. Such a junction can be switched
between the two states of electrical resistance, one with low
resistance, and other with very high resistance.
The MTJ and MRAM cell can be modeled and realized in
several ways, depending upon the performance of the device
and the materials used. The electrical behavior of an MTJ can
be realized and implemented using a SPICE sub-circuit which
is capable to exhibiting the same performance as an MTJ,
which can be further used to implement a D flip flop, where
the MTJ is used as a data storage element[1]
. The STT MRAM
can be driven by using an asymmetrical vertical silicon gate
Nano-wire gate all around select device (GAA select device)
using Verilog-A. Perpendicular magnetic anisotropy (MTJ)
multilayer structure is stacked above the GAA select device
and the asymmetry in the critical switching current of an MTJ
is exploited by a matching asymmetric drive current select
device that can be helpful in achieving significant reduction in
the power dissipation [2]
. The proposed design targets to attain
the optimistic figure of 4F2
array density, where F is the
feature size, and 4F2
is the maximum 2-D density which can
be achieved. A 4F2
buried-source-line STT MRAM cell
structure with vertical gate all around, cylindrical buried
source NMOS transistor is proposed. The magnetic tunnel
junction multi-layer structure is stacked above the select
device, where both occupy the same 2-D area [3]
. A non-
volatile memory based on STT-MTJ used as a Spintronics
device for Field Programmable Gate Array (FPGA) and
System on Chip (SoC) circuits is presented, which makes the
device fully non-volatile by permanently storing all the data
processed in the Spin-MTJ cells [4]
. Three nonvolatile flip-flop
(FF)/SRAM cells utilizing a single magnetic tunneling

2. junction as nonvolatile resistive element are proposed. These
cells have the same core (6T) but employing different numbers
of MOSFETs to implement the instantly ON, normally OFF
operation mode. Additional transistors have been utilized for
the restore operation to make sure that the data stored in the
circuitry can be written back into the FF core once the power
is made available to it [5]
.
II. PROPERTIES OF MTJ
1. MTJs are typically current controlled devices. That is
the resistance of the MTJ is directly dependent on the
current through it. An MTJ aligns its magnetic
orientation in parallel state (low resistance) if the
current flows from the fixed terminal to the flexible
terminal, in anti-parallel state (high resistance) if the
current flow is from the flexible terminal to the fixed
terminal. Hence, conventionally the bit stored is said
to be “1” if the MTJ is in parallel (low resistance
state) and “0” if the MTJ is in anti-parallel (high
resistance) state.
2. The critical switching currents for both the parallel
and anti-parallel states are different indicating that
the switching effort involved in the two switches are
different [2]. With each switching, a switching time
is associated and is given by the relation[1],
Icrit = ICrit0 [1 – kB*T/E* ln(tp/t0)]
Where, „ICrit0‟ is the critical switching current for
the respective states.
3. Each MTJ is associated with a parameter called TMR
ratio, given by
TMR = ( Rap – Rp ) / Rp
Where Rp is the resistance of MTJ in parallel state
and Rap is the resistance of MTJ in anti-parallel state.
III. THE MACRO MODEL OF THE MTJ IN HSPICE
In this work, the electric behavior of the MTJ is modeled in
HSPICE. The model was built by using voltage controlled
resistances, various current, muxes, capacitors and amplifiers.
The following section describes the basic components of the
macro-model.
A. Electrodes:
The MTJ is basically a two terminal device. One of
them is considered as fixed terminal and the other the
flexible terminal; meaning its magnetic orientation is
flexible. In this model, we have started by connecting
a voltage controlled resistor between the two
electrodes of the device. The control signal for this
resistor is generated by using a control circuitry. A
small capacitance is also modeled between the
terminals to account for the parasitic effects.
B. Circuit for Decision making:
In the modeling of MTJ it is necessary to come up
with a decision mechanism to accurately switch
between the high resistance and low resistance states.
In this stage, the current through MTJ is first
sampled. The sampled value is then compared with
the standard switching currents for parallel and anti-
parallel states. The two standard switching currents
are modeled using current sources representing the
switching values. Based on this comparison, an
output signal is generated that tells whether to switch
the MTJ to parallel state or anti-parallel state. The
behavior of the decision circuit modeled using
current sources and mux is as follows:
Vdecision = +1 V, when IMTJ > Ip
= -1 V, when IMTJ < Iap
The critical currents for parallel [Ip] and anti-parallel
[Iap] switching are 325uA and -425uA respectively
[1] .The decision works such that if the last decision
was 1V then the MTJ should switch to anti-parallel
state; If the last decision was -1V then the MTJ
should switch to parallel state.
C. The Bi-stable amplification stage:
The bi-stable circuit is used to indicate the present
state of the MTJ device. This stage is modeled by
using the bi-stable amplifier circuit and a feedback
circuit to input the initial condition of the MTJ to be
parallel or anti-parallel. In this work, the initial state
of the MTJ is modeled to be in the anti-parallel state.
The capacitor feedback loop was used in the design.
The behavior of the bi-stable element can be
described as follows
Vstate = +10 V, when last Vdecision was −1 V
= -10 V, when last Vdecision was +1 V
Here the voltage level +10 represents the antiparallel
or the high resistance state and the voltage level -10
represents the parallel or low resistance state.
D. Curve fit circuit:

3. The curve fitting circuit is designed to generate the
final control voltage for the switching of the voltage
controlled resistor connected between the two
terminals of the MTJ. The fitting circuit used in this
design is of Gaussian profile. It is designed in such a
way as to allow the designer to state the parallel and
anti-parallel resistance values required in the design
in the fitting curve. The behavior of the curve fitting
circuit for Gaussian profile can be modeled as
follows
Vctrl = 1 V, when Vstate is −10 V
= (RAP/ RP )× 1 V, when Vstate is + 10 V
The control voltage is scaled to make the output lie
within the TMR ratio of MTJ. For this design, we
have used standard parallel and anti-parallel
resistance as 1.8kΩ and 4.5kΩ respectively[1]. The
Gaussian curve fitting equation is given by,
Vo = Vctrl × exp(-VMTJ ^2/2c^2).
Where c^2 is the curve fitting parameter, given by the bias
voltage that makes Vo to drop to 30% of its original value.
The signal Vo is the final control voltage that controls the
switch between the states.
IV. TYPICAL MRAM CELL
The typical MRAM cell can be formed by using one NMOS
that acts as a select device and one MTJ. The select device is
used to activate or deactivate the MTJ device as and when
required by the design. The select device are designed to
provide good access times and better driving currents for the
MTJ[2]. The structure of 1T MRAM cell is sown in figure 1.
Fig 1.Typical 1T MRAM cell
The flexible electrode of the MTJ is connected to bit line
(BL). The basic structure can be replicated in both directions
to obtain an array of MRAM cells.
V. SIMULATION RESULTS
The macro modeling of MTJ was carried out in HSPICE. The
standard values of critical currents (Ic0) and other parameters
used for the design are listed in the table below [1].
SL NO PARAMETER VALUE
1. Ic0 (Parallel) 3.25uA
2. Ic0 (Antiparallel) -4.25uA
3. Rp 1.8K Ω
4. Rap 4.5 K Ω
5. Initial state Anti-parallel
Table1. Standard values used in the design [1]
Fig 2: MTJ simulated using a triangular current source
The model was simulated using a triangular current source of
various pulse widths to verify the resistance switching
characteristics. The resistance of the MTJ is found to switch
between 1.8KΩ and 4.5KΩ with the critical currents specified
in the design. The working of the macro model was verified
by observing the fact that the device switched to anti-parallel
mode (high resistance) when the current across MTJ is greater
than critical switching current of 325uA and vice versa

4. Fig 3: 1T MRAM cell (Read, write and hold operations)
Fig 4: 2X2 MRAM cell (read, write, hold operations)
Fig 5: 2X2 MRAM cell (read, write, hold operations)
Fig 6 : 2X2 MRAM cell (read, write, hold operations)
Fig 7: 2X2 MRAM cell (read, write, hold operations)
The figure 2 shows the read, write and hold operation of the
single transistor MRAM cell modelled in the 45nm
technology. The antiparallel state (high resistance) represents
the bit 0 and the parallel state (low resistance) represents the
bit 1. The MRAM cell is designed as represented in fig 1. The
cell is active whenever the word line (WL) is asserted.
Initially, the MTJ will be in the anti parallel state as designed
for this work. A bit „1‟ is stored by making the bit line (BL)
high and select line (SL) low so that the current flow is from
the fixed electrode of MTJ to the flexible electrode. This
makes the MTJ to align to parallel or low resistance state
indicating the stored bit „1‟. A bit 0 is stored by making the bit
line (BL) low and select line (SL) high so that the current flow
is from the flexible electrode of MTJ to the fixed electrode.
This makes the MTJ to align to anti parallel or high resistance
state indicating the stored bit „0‟. The read operation is
performed by pre charging the bit line (BL) to the optimum
pre charge value of 0.4 V [2] and asserting the word line
simultaneously.
The MRAM array can be formed by replicating this basic
structure in both dimensions. The figure 3, 4, 5 and 6 verify
the working of 2X2 MRAM memory array. The structure can
be similarly replicated to obtain NXN memory array.
VI. RESULT AND DISCUSSION
The Magnetic tunnel Junction (MTJ) was modeled in the
HSPICE tool. The model was built by using voltage controlled
resistances, various current, muxes, capacitors and amplifiers.
The resistance of the device was designed to switch between
1.8k Ω and 4.5k Ω with the standard switching currents for
parallel and anti-parallel states. The model was simulated
using a triangular current wave of various pulse widths to
verify the resistance switching characteristics. The usefulness
of the modeled MTJ as a non-volatile memory element was
proposed by designing a 1T MRAM cell and verifying the
read, write and hold operation. A basic 2X2 MRAM array
structure was similarly designed to emphasize the fact that the
scope of the designed cells can be extended by replicating
them in both dimensions to design an NXN MRAM memory
array.

5. REFERENCES
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[2] Shivam Verma, Sanjay Mahawar and Brajesh Kumar Kaushik,” Low
Power STT MRAM Cell With Asymmetric Drive Current Vertical GAA
Select Device”
[3] Shivam Verma, Shalu Kaundal, Student Member and Brajesh Kumar
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