This document discusses operands and addressing modes in computer architecture. It describes different types of operands including register operands that specify a register, immediate operands that specify a constant value, and memory operands that specify an address using a base register, index register, scale, and displacement. It also describes different addressing modes like direct addressing that uses a displacement and register indirect addressing that uses the contents of a base register as an offset.

1. Operands & Addressing Modes
Dr Philip Leong
phwl@doc.ic.ac.uk
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 1)

2. Addressing modes
addr is address field of instruction
Immediate addr is operand
Register addr is register number in CPU
– operand := [ addr ]
Direct addr is address in primary (main) memory
– operand := [ addr ]
Indirect addr is register number (or memory address)
– operand_address := [ addr ]
operand [ operand_address ]
Indexed addr is base address, index is a register
– operand := [ addr + [ index ] ]
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3. Instructions
Two Operand Instructions
Label: OPCODE Destination, Source ; Comments
Single Operand Instructions
Label: OPCODE Operand ; Comments
Zero Operands Instructions
Label: OPCODE ; Comments
Label is a user-defined identifier that is defined by the address of the
instruction or item of data that follows.
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4. Operands (Addressing Modes)
Register Operands
e.g. EAX, DX, AL, SI, BP, DS
Immediate Operands (Constants)
e.g. 23, 67H, 101010xB, ‘R’, ‘ON’
Memory Operands
[ BaseReg + Scale * IndexReg + Displacement ]
e.g. [24], [BP], [ESI+2], [BP + 8 * DI + 16]
Source and Destination operands cannot both be a memory operand.
Note: Some instructions use particular registers implicitly.
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5. Directives
Most assemblers allow “global” variables to be allocated and defined
symbolically with a data definition directive, e.g.
MaxElem DW ? ; allocates a word
Users DB 3 ; allocates a byte with initial value 3
Total DD ? ; allocates a doubleword
Message DB “hello” ; allocates 5 bytes with text value hello
Sequence DW 1, 2, 3 ; allocates 3 words with values 1, 2 and 3
List DW 50 DUP (0) ; allocates 50 words initialised to 0
Most assemblers also allow constant values to be defined symbolically:
Age EQU 22
MyPointer EQU 1000
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6. Examples
Label Instruction Comment
MOV AH, CL ; AH := CL
ADD AX, [BX] ; AX := AX + Memory [DS:BX]
MOV AX, [BP+4] ; AX := Memory[SS:BP+4]
ADD AX, ES:[BX] ; AX := AX + Memory [ES:BX]
SUB EAX, 45 ; EAX := EAX - 45
MOV BYTE PTR [BX] , 45 ; Memory [DS:BX] := 45
ADD CH, [22] ; CH := CH + Memory [DS:22]
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7. More Examples
Label Instruction Comment
CMP EAX, ECX ; Compare operands and Set
; EFLAGS register
JE forlabel ; if FLAGS.ZF = 1 then
; EIP := forlabel
forlabel: NEG AX ; AX := -AX
CALL print ; Call procedure print
RET ; Return from procedure
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8. Register Operand
Register
Operand found in the specified Depending on the instruction and
register processor, the operands can be
located in any of the General
Purpose Registers, Base and Index
MOV AX, DX Registers, Segment Registers,
MOV AH, BL FLAGS Register
MOV SP, BP Some instructions such as IMUL and
IDIV implicitly use operands
MOV DS, AX contained in a pair of registers, e.g.
MOV EDI, ESI in AX and DX.
In most cases Dest & Source
MOV ES, DS ; Disallowed operands must be of the same size
Seg. Reg to Seg. Reg moves are not
MOV CS, AX ; Disallowed
allowed. Cannot move to CS either.
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9. Immediate (Constant) Operand
Constant
Operand is an immediate Immediate values are encoded
(constant) value directly into the instruction.
Not normally applicable for
MOV AX, 22 Destination Operand
MOV AX, 16H
Doubleword constants on Pentium
MOV AX, 10110xB only
MOV EBX, 12345678H
MOV BX, Age
MOV AL, ‘A’
MOV AX, ‘MP’
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10. Memory Operands
Specify an address offset (effective address) using expressions of the
form (different parts of expression are optional):
[ Base Register + Scale * Index Register + Displacement ]
1) Base Register (EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI)
(only BX or BP on 8086)
2) Index Register (EAX, EBX, ECX, EDX, EBP, EDI, ESI)
(only SI or DI on 8086)
Scale 2 or 4 or 8 (Pentium only)
3) Displacement (constant value)
Size of operand is normally inferred from Instruction or 2nd operand if
register. We can explicitly prefix operand with BYTE PTR or WORD PTR
or DWORD PTR.
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11. Default Segments
Type of Default Default Selection Rule
Reference Segment
Data Data (DS) All data references, except
stack references & string instruction
destination references
Stack Stack (SS) All stack pushes & pops (via ESP)
References which use EBP
as Base Register
String Dest Extra (ES) Destination operand of string
instructions.
Instructions Code (CS) All instruction fetches
Default Segments can usually be overridden e.g. ES:[EBP+2]
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12. Displacement (Direct Addressing)
[ Displacement ]
Specified constant value (called Displacements are encoded
the displacement) gives offset. directly into the instruction.
Allows global variables with fixed
MOV AX, [22] offset values to be addressed
MOV AX, ES:[22] directly.
MOV [16H] , AX
MOV BYTE PTR [22] , 98
MOV EBX, [12345678H]
MOV CX, Users
MOV [MyPointer], AH
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13. Example 1: MOV AX, [22]
AX
-637
Data Segment
(e.g. DS * 16) 0
+22 2 ...
22
22 -637
Instruction
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14. Example 2: MOV AX, ES:[22]
AX
+738
Extra Segment
(e.g. ES * 16) 0
+22 2 ...
22
22 +738
Instruction
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 14)

15. Example 3: MOV BYTE PTR [22], 98
Instruction
98
Data Segment
(e.g. DS * 16) 0
+22 2 ...
22
22 98
Instruction
24 MOV WORD PTR [26], 99
26 99
99
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16. Base (Register Indirect)
[ Base ]
Contents of specified Base Pentium: EAX, EBX, ECX, EDX,
Register gives offset. ESP, EBP, EDI, ESI
8086: BX, BP, DI, SI
MOV AX, [BX]
MOV [BP], AL Since the value in the Base
MOV AX, [DI] Register can be updated, it can
MOV [SI] , AH be used to dynamically address
(point to) variables in memory,
MOV EBX, [ESI]
e.g. array elements, linked lists,
MOV [EAX], ECX trees.
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17. Example 1: MOV AX, [BX]
AX
-100
Data Segment
0
2
+66 ...
BX 66 -100
66
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18. Example 2: MOV [BP], AL
AL
55
Stack Segment
(e.g. SS * 16) 0
2
+12 ...
BP 12 55
12
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19. Base + Displacement (Register Relative)
[ Base + Displacement ] or Displacement [ Base ]
Sum of specified Base Register Pentium: EAX, EBX, ECX, EDX,
and Displacement gives offset. ESP, EBP, EDI, ESI
Displacement can be negative. 8086: BX, BP, DI, SI
Can be used to access record
MOV AX, [BX+4] fields, e.g. Base Register = start of
MOV [BP+2] , DH record, Displacement = position of
MOV AX, [DI–6] field.
MOV DL, [SI+Age] Can be used to access array
elements, e.g. Displacement = start
MOV AH, [EAX+12] of array, Base Register = position
MOV List [BX] , CX of element
MOV DX, List [BP–2] Can be used to access parameters
& local variables.
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20. Example 1: MOV AX, [BX+4]
AX
2244
Data Segment
0
BX 2
+12 ...
12 BX points to Start
of a Record with
+4 12 X fields X, Y & Z
Y
4 +4 selects field Z
16 2244
Instruction
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 20)

21. Example 2: MOV AX, [BX+4]
AX
Data Segment
-99
+4 0
2
Instruction
4 A[0]
+4 6 A[1]
+12 8 A[2] +4 points to start of
10 A[3] an Array
BX 12 A[4]
14 A[5] BX holds “index” to
12 array element
16 -99
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 21)

22. Base + Index (Based Indexed)
[ Base + Index ] or [ Base ] [ Index ]
Sum of specified Base Register Pentium: EAX, EBX, ECX, EDX,
and Index Register gives offset ESP, EBP, EDI, ESI
MOV CX, [BX + DI] 8086: Base Reg = BX, BP
MOV [EAX + EBX] , ECX Index Reg = DI, SI
MOV CH, [BP] [SI]
Can be used to access array
MOV [BX] [SI] , SP
elements, e.g. Base Register =
MOV CL, [EDX] [ EDI] start of array, Index Register =
MOV [EAX] [EBX] , ECX position of element.
MOV [BP + DI] , CX
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23. Example: MOV AX, [BX+DI]
AX
-27
Data Segment
0
BX +12 2 ...
12
Start of Array
12 A[0]
DI +6 14 A[1]
6 16 A[2]
DI is index to 18 -27
array element
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24. Base + Index + Displacement (Based Relative Index)
[ Base + Index + Displacement]
Sum of specified Base Register Pentium: EAX, EBX, ECX, EDX,
and Index Register and EBP, EDI, ESI
Displacement gives offset
8086: Base Reg= BX, BP
Alt Syntax: Index Reg = DI, SI
Disp1 [Base] [Index+Disp2]
Displacement = Disp1+Disp2
Also known as Relative Based
MOV AX, [BP+DI+10] Index
MOV DH, [BX][DI-6] Can be used to access local
MOV AX, List [BX][DI] (stack) arrays, arrays of
MOV List [BP][DI–64], DX records, 2D arrays.
MOV EAX, List [EBX][ECX+2]
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25. Example: MOV AX, [BP+DI+10]
Stack Segment AX
0
BP +12 +67
...
12
12
+10
+10
Instruction 22 A[0] BP+10 points to start
+6 24 A[1] of array on stack
26 A[2]
6 28 +67 DI holds “position” of
array element
DI
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26. (Scale*Index) + Displacement (Scaled Index)
[ Scale * Index + Displacement]
Product of Index Register and a Only Pentium
constant scaling factor (2, 4 or
8) added to specified Supports efficient access to
Displacement to give offset. array elements when the element
size is 2, 4 or 8 bytes, e.g.
MOV EAX, [4 * ECX + 4] Displacement = offset to
MOV List [2 * EBX], CX beginning of array.
MOV List [2 * EBX+32], DX Index Register = position of
MOV AX, [2 * EDI+Age] desired element,
Scale = element size in bytes
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27. Example: MOV AX, ES:[2*ECX+4]
AX
Extra Segment
-99
+4 0
2
Instruction
4 A[0]
+4 6 A[1]
8 A[2]
+(2*6) 10 +4 points to start of
A[3] a Array
ECX 12 A[4]
14 A[5] ECX holds position of
6 array element
16 -99
Elements = 2 bytes
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28. Base + (Scale * Index) + Displacement
[ Base + Scale * Index + Displacement]
Product of Index Register and a Known as Based Scaled Index
constant scaling factor (2, 4 or
8) added to specified Base Only Pentium
Register and Displacement to
give offset.
Supports efficient access to
MOV EAX, [EBX][4*ECX] local arrays on the stack when
the element size is 2, 4 or 8
MOV [EAX][2*EBX] , CX
bytes.
MOV AX, [EBP][2*EDI+Age]
MOV List[EAX][2*EBX+32], DX
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 28)

29. Example: MOV EAX, [EBX+4*EDX+10]
Data Segment EAX
0
EBX +12 12349908H
...
12
12 EBX points to start
+10 of record
+10
EBX+10 points to
Instruction 22 A[0] start of array within
+(4*2) 24 A[0] record
26 A[1] EDX holds “position”
2 28 A[1] of array element.
EDX 30 9908H Elements = 4 bytes
32 1234H
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30. Think about
1. Why zero, single and two operand instructions occur in the
8086 instruction set.
2. The difference between a directive and an assembly
language statement
3. The difference between all of the addressing modes
4. How high level language statements like a = b[5]+c are
translated to assembly language and what addressing modes
are used
5. The machine organisation required to handle the addressing
modes
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 30)