The document discusses basic I/O in the 8085 microprocessor, including memory interfaces and devices. It describes the common components of memory, such as address pins to select locations, data pins for reading and writing, selection pins to enable operations, and control pins. The main types of memory discussed are ROM, RAM, EPROM, and examples of addressing schemes using decoders to map memory chips into the microprocessor's address space.

1. BASIC I/O IN 8085

2. Memory Interface
◦ Every microprocessor-based system has a memory system
◦ Two basic types:
1. Read-only memory (ROM): It
stores system software and permanent system data
2. Random access memory (RAM):
It stores temporary data and application software (data and instructions)
Four commonly used memories:
1. ROM
2. Flashable EEPROM
3. Static RAM (SRAM)
4. Dynamic RAM (DRAM), SDRAM, RAMBUS, DDR RAM

3. Memory Devices
◦ Generic PIN configuration

4. Address Pins
◦ All memory devices have address inputs.
◦ Select a memory location within the memory device.
◦ The number of address pins is related to the number of memory locations.
Common sizes today are 1K to 256M locations.
Therefore, between 10 and 28 address pins are present.
◦ Address inputs are labeled from A0 to AN.
◦ N is the total number of address pins minus 1.
◦ Example: The 2K memory:
has 11 address lines.
labels are (A0 - A10).
the start address is 10000H so the end address is:
10000H + ((2*1024)10 = 800H)=107FFH

5. Data Pins
◦ All memory devices have a set of data outputs or input/outputs.
◦ Used to enter the data for storage or extract the data for reading.
◦ The data pins are typically bi-directional in read-write memories.
The number of data pins is related to the size of the memory location
For example, an 8-bit wide (byte-wide) memory device has 8 data pins.
Catalog listing of 1K X 8 indicate a byte addressable 8Kbit memory with 10 address pins.
◦ Memory devices are defined by memory locations times bit per location.
◦ Example: 1K x 8, 16K x 1, 64K x 4.

6. Selection Pins
◦ Each memory device has at least one chip select(𝐶𝑆) or chip enable(𝐶𝐸) or select(𝑆) pin that
enables the memory device.
This enables read and/or write operations.
If more than one are present, then all must be 0 in order to perform a read or write.
◦ If they are active (logic 0), the memory device performs a read or write operation.
◦ If they are inactive (logic 1), the memory is disabled and do not do any operation.
◦ If more than one selection connection is present. All must be activated to read or write.

7. Control Pins
◦ Each memory device has at least one control pin
◦ For ROMs, an Output Enable (𝑂𝐸’) or Gate (𝐺) is present.
◦ The 𝑂𝐸’ pin enables and disables a set of tri-state buffers.
◦ For RAMs, a read-write(R/𝑊’) or write enable(𝑊𝐸’) and read enable(𝑂𝐸’) are present.
◦ For dual control pin devices, it must be hold true that both are not 0 at the same time.

8. ROM
◦ Non-volatile memory: Maintains its state when powered down.
◦ The 27XXX series of the EPROM includes:
◦ Each EPROM has:
◦ Address Pins
◦ 8 data connections
◦ One or more selection inputs and one output enable pins
2704 (512 x 8) 2708 (1K x 8)
2716 (2K x 8) 2732 (4K x8)
2764 (8K x 8) 27128 (16K x 8)
27256 (32K x 8) 27512 (64K x 8)
271024 (128K x 8)

9. Memory Address Decoding
◦ The processor can usually address a memory space that is much larger than the memory space
covered by an individual memory chip.
◦ In order to splice a memory device into the address space of the processor, decoding is
necessary.
◦ For example,
1. The 8088 issues 20-bit addresses for a total of 1MB of memory address space.
2. The BIOS on a 2716 EPROM has only 2KB of memory and 11address pins.
3. A decoder can be used to decode the additional 9 address pins and allow the EPROM to be
placed in any 2KB section of the 1MB address space.

10. NAND Decoder Example

11. NAND Decoder Example
◦ To determine the address range that a device is mapped into
◦ NAND gate decoders are not often used
Large fan-in NAND gates are not efficient
Multiple NAND gate IC's might be required to perform such decoding
Rather the 3-to-8 Line Decoder (74LS138) is more common.

12. The 3-to-8 Line Decoder (75LS138)

13. Sample Decoder Service

14. A simple example
◦ Let’s assume a very simple microprocessor with 10 address lines (1KB memory)
◦ Let’s assume we wish to implement all its memory space and we use 128x8 memory chips
We will need 8 memory chips (8x128=1024)
We will need 3 address lines to select each one of the 8 chips
Each chip will need 7 address lines to address its internal memory cells

15. Decoding example

16. Thank You