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Operating Systems 1 (2/12) - Hardware Basics
The document discusses the basics of hardware and operating systems, including various classes of operating systems such as embedded and real-time systems. It covers key concepts like processes, memory management, I/O operations, and multiprocessor architectures, emphasizing the importance of efficiency and the organization of memory in a hierarchy. Additionally, it outlines the role of interrupts and the challenges modern operating systems face with evolving hardware technology.
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Operating Systems 1 (2/12) - Hardware Basics
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- 2. Operating Systems IPT / FF 14 Computer Systems Today 2 Users Application Programs System Programs Operating System Firmware Hardware Controlexecution ofprograms Abstractfrom hardware
- 3. Operating Systems IPT / FF 14 Classes of Operating Systems • Desktop / Server Operating Systems • Distributed Operating Systems • Implements a single operating system instance spanning multiple machines • Applications have single memory space view • No significant real-world adoption, mainly research topic • Real-Time Operating System (RTOS) • Deterministic timing behavior of operating system services • Support for real-time application scheduling and resource management • Wide adoption for industry applications • Examples: LynxOS, OSE, QNX, RTLinux, VxWorks • Embedded Operating System 3
- 4. Operating Systems IPT / FF 14 Main Concepts • Processes • Process table, core image, fork, command interpreter, shell, child processes, scheduling, signals, user authorization, group identification, process tree, ... • Memory • Swapping, paging, segmentation, virtual address, security, device access, ... • I/O • Files, directories, root directory, working directory, path, protection, rwx bits, file descriptor, handle, special files, I/O devices, block I/O, character I/O, standard input/output/error, pipes, mailslots, sockets, ... • ... all abstracting hardware concepts to some extend 4 Main Concepts:Main Concepts: pprorocecessessess ProProccesseessess, process table, core image, process table, core image Command interpreter, shellCommand interpreter, shell Child processesChild processes A B C 41 Scheduling, signalsScheduling, signals User identification, group identificationUser identification, group identification ready running blocked finishednew B C FED Process tree Main Concepts:Main Concepts: pprorocece ProProccesseessess, process table, core, process table, core Command interpreter, shellCommand interpreter, shell Child processesChild processes Scheduling, signalsScheduling, signals User identification, group identifUser identification, group identif ready running blocked finishednew Main Concepts:Main Concepts: FilesFiles Files, directories, rootFiles, directories, root Path, working directoryPath, working directory Protection, rwx bitsProtection, rwx bits File descriptor, handleFile descriptor, handle Root directory tmp usretc 42 File descriptor, handleFile descriptor, handle Special files, I/O devicesSpecial files, I/O devices Block I/O, character I/OBlock I/O, character I/O Standard input/output/errorStandard input/output/error pipespipes pitmia
- 5. Operating Systems IPT / FF 14 Hardware Basics 5
- 6. Operating Systems IPT / FF 14 Hardware Basics • Central Processing Units (CPUs) + volatile memory + I/O devices • Fetch instruction and execute it - typically memory access, computation, and / or I/O 6 (C) Stallings • I/O devices and memory controller may interrupt the instruction processing • Improve processor utilization by asynchronous operations
- 7. Operating Systems IPT / FF 14 Hardware Basics • Symmetric Multi-Processing (SMP) • Two or more processors in one system, can perform the same operations (symmetric) • Processors share the same main memory and all devices • Increased performance and scalability for multi-tasking • No master, any processor can cause another to reschedule • Multi-Core / many-core processor combines computational cores on one chip with shared caches • Challenges for an SMP operating system: • Reentrant kernel, scheduling policies, synchronization, memory re-use, ... 7 (C) Stallings
- 8. Operating Systems IPT / FF 14 Hardware Basics • Multi-Programming vs. multi-processing 8
- 9. Operating Systems IPT / FF 14 Hardware Basics • Hyperthreading • Make a single processor appear to be two virtual processors by maintaining separate CPU states, while execution engine and caches are still shared • Also called Simultaneous multithreading (SMT) • Operating systems must consider them separately in scheduling (in Windows since XP) 9 (C) Intel
- 10. Operating Systems IPT / FF 14 Hardware Basics • Parallelism • Inside the processor (instruction-level parallelism, multicore) • Through multiple processors in one machine (multiprocessing) • Through multiple machines (multicomputer) 10 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! "#$%&'()! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! *)#+(,,#)!"-.%! ! ! ! ! ! "#$%&'/'.#0/1! 203.0(! 4/,5! 4/,5! 4/,5! 4/,5! !"#$% &"'"(()(*#+% ,-#.'/0.*1-% 2.')"+% 6#3.+/1!! *)#+(,,#)! 6#3.+/1! *)#+(,,#)! "-.%!7&1'.84-)(/9.03!:"74;! <=$$(').+!7&1'.8*)#+(,,.03!:<7*;! 7&1'.+#$%&'()! ! ! ! ! ! "#$%&'/'.#0/1! 203.0(! 6#3.+/1! *)#+(,,#)! 6#3.+/1! *)#+(,,#)! *)#+(,,#)!"-.%! >>>! >>>! "#$%&'()! "-.%!7&1'.8*)#+(,,.03!:"7*;! >>>! <.$&1'/0(#&,! 7&1'.84-)(/9.03! :<74;! ?0,')&+'.#086(@(1! %/)/11(1.,$!:?6*;! A/'/! A/'/! A/'/! A/'/! 3"."% &"'"(()(*#+% % % Figure 1: Hardware parallelism hierarchy
- 11. Operating Systems IPT / FF 14 Hardware Basics 11 Intel Core i7 SPARC64™ VIIIfx 12 SPARC64™ VIIIfx • • • • Core5 Core4 Core1 Core0 Core7 Core6 Core3 Core2 DDR3interface DDR3interface L2$ Data L2$ Data HSIO L2$ ControlMAC MAC MAC MAC SPARC64 VIIIfx
- 12. Operating Systems IPT / FF 14 Hardware Basics • NUMA (non uniform memory architecture) systems • Groups of physical processors (called “nodes”) that have local memory • Connected to the larger system through a cache-coherent interconnect bus • Still an SMP system (e.g. any processor can access all of memory), but node-local memory is faster • Operating system tries to schedule close activities on the same node • Became the default model in all recent architectures 12 Processor A Processor B Cache Cache Memory Processor C Processor D Cache Cache Memory High-Speed Interconnect
- 13. Operating Systems IPT / FF 14 Hardware Basics 13 Core Core Core Core Q P I Core Core Core Core Q P I Core Core Core Core Q P I Core Core Core Core Q P I L3CacheL3Cache L3Cache MemoryController MemoryControllerMemoryController L3Cache MemoryController I/O I/O I/OI/O MemoryMemory MemoryMemory Intel Nehalem
- 14. Operating Systems IPT / FF 14 Hardware Basics • Major constraints in memory as a resource are amount, speed, and costs • Faster access time results in greater costs per bit • Greater capacity results in smaller costs per bit • Greater capacity results in slower access • Idea: Going down a memory hierarchy • Decreasing costs per bit • Increasing capacity for fixed costs • Increasing access time 14 http://tjliu.myweb.hinet.net/
- 15. Operating Systems IPT / FF 14 (C) Stallings Hardware Basics • Principle of Locality • Memory referenced by a processor (program and data) tends to cluster • Iterative loops and subroutines, small set of instructions inside • Operations on tables and arrays involve access to clustered data sets • Data should be organized so that the percentage of accesses to lower levels is substantially less than to the level above • Typically implemented by caching concept • I/O devices provide non-volatile memory on lower levels, which is an additional advantage 15
- 16. Operating Systems IPT / FF 14 Hardware Basics • Caching • Offer a portion of lower level memory as copy in the faster smaller memory • Leverages the principle of locality • Processor caches work in hardware, but must be considered by an operating system 16 (C) Stallings
- 17. Operating Systems IPT / FF 14 Hardware Basics • Conflicting caching design goals • Cache size per level • Number of cache levels • Block size exchanged with lower level memory • Replacement algorithm • Mapping function • Write policy for modified cache lines • All decisions made by hardware vendor, considerable by software 17 (C) Stallings
- 18. Operating Systems IPT / FF 14 Hardware Basics • All computers have mechanisms to let I/O and memory modules interrupt the current processor work • Consider the speed aspect of I/O devices in the memory hierarchy • Different classes of interrupt • Program interrupt: Condition from program execution leads to exceptional situation, such as arithmetic overflow, division by zero, illegal instruction • Timer interrupt: Programmed hardware time signals the time event, e.g. for regular operating system activities • I/O interrupt: Generated by any kind of hardware unit to signal I/O completion or an error condition • Hardware failure interrupt: Hardware module signals permanent issue 18
- 19. Operating Systems IPT / FF 14 Hardware Basics 19 • I/O program prepares an I/O operation, waits for finalization and prepares the result for further processing • Usage of interrupts reduces the application I/O wait time to the pre- and post phases of I/O processing • Interrupt can occur at any point in the execution of the user program, must be managed by the operating system
- 20. Operating Systems IPT / FF 14 Hardware Basics 20
- 21. Operating Systems IPT / FF 14 Hardware Basics • Summary • Modern operating systems have to deal with many execution units (cores) and processors (SMP) in the same box • Memory is organized in a deep hierarchy • Differences in speed and amount at the order of magnitudes • Devices and other sources can interrupt the current processing at any point • All of this is permanently changing • New processors, memory technology, hardware devices, ... • Operating system must allow applications to use old and new hardware • Example: Windows Vista supports approx. 4200 printers out of the box 21
- 22. Any problem incomputer science can be solved with another layer of indirection. But that usually will create another problem. David Wheeler