7.1 flip flops

Asignatura: Electrónica Digital
Mgtr: José A. Rumipamba López
DIGITAL SYSTEMS, 10ª EDICIÓN
5.1 Nand gate latch - 5.2 Nor gate latch
Mgtr. José A. Rumipamba López
1

The logic circuits considered thus far have been combinational circuits whose
output levels at any instant of time are dependent on the levels present at the
inputs at that time.
2

 The figure shows a block diagram of a general digital system that combines
combinational logic gates with memory devices.
3
General digital
system diagram.

 The most important memory element is the flip-flop (FF), which is made up of an
assembly of logic gates.
4

 If we say that a FF is in the HIGH (1) state, we mean that Q=1.
 If we say that a FF is in the LOW (0) state, we mean that Q=0.
 Of course, the state will always be the inverse of Q.
5

 Whenever the inputs to a FF cause it to go to Q=1 the state, we call this setting the
FF; the FF has been set.
 Whenever the inputs to a FF cause it to go to Q=0 the state, we call this clearing or
resetting the FF; the FF has been cleared (reset).
6

FF’s memory characteristic:
 We will find out that most FF inputs need only to be momentarily activated (pulsed)
in order to cause a change in the FF output state, and the output will remain in that
new state even after the input pulse is over.
7

 The flip-flop is known by other names, including latch and bistable multivibrator.
8

Asignatura: Electrónica Digital
Mgtr: José A. Rumipamba López
9


 The NAND gate version, called a NAND gate latch or simply a latch is the most
basic FF circuit can be constructed from two NAND gates.
10

11
One possibility Second possibility
 This condition is the normal resting state, and it has no effect on the output state.
 The Q and 𝑸 outputs will remain in whatever state they were in prior to this input
condition.

Setting the Latch (FF)
12
SETTING

Resetting the Latch (FF)
13
CLEARING OR RESETTING

Simultaneous Setting and Resetting
14
 This will produce HIGH levels at both NAND outputs so that 𝑸 = 𝑸 = 𝟏.
 Clearly, this is an undesired condition because the two outputs are supposed to be
inverses of each other.
 For these reasons the SET = RESET = 0 condition is normally not used for the
NAND latch.

15
Mechanical contact bounce will produce multiple transitions

16
NAND latch used to debounce a mechanical switch


 The NOR gate version, called a NOR gate latch or simply a latch is the most basic
FF circuit can be constructed from two NOR gates.
17

 The analysis of the operation of the NOR latch can be performed in exactly the
same manner as for the NAND latch.
18

19
The figure shows a simple circuit that can be used to detect the interruption of a
light beam. Assume that the latch has previously been cleared to the 0 state by
momentarily opening switch SW1.

20
Rise time Fall time
width

21
 When a microcontroller wants to access data in its external memory, it activates an
active-LOW output pin called (read).The data book says that the pulse typically has
a pulse width of 50 ns, a rise time of 15 ns, and a fall time of 10 ns.

 The waveforms of next figure are applied to the inputs of the NAND gate latch and
of the NOR gate latch. Assume that initially Q = 0, and determine the 𝑸 and 𝑸
waveform.
22

7.1 flip flops

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7.1 flip flops