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Subject: Digital Electronics
Mgtr: José A. Rumipamba López
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
1
2
 Is generally equal to the number of states that the counter goes through in each
complete cycle before it recycles back to its starting state.
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
3
N is the number of FFs
 In any counter, the signal at the output of the last FF (i.e., the MSB) will have a
frequency equal to the input clock frequency divided by the MOD number of the
counter.
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
4
For example, in a MOD-16 counter, the output from the
last FF will have a frequency of 1/16 of the input clock
frequency
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
5
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
6
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
7
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
8
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
9
 To construct a counter that starts counting from all 0s and has a MOD number of X:
1) Find the smallest number of FFs such that 𝟐 𝑵 ≥ 𝑿, and connect them as a
counter.
2) Connect a NAND gate to the asynchronous CLEAR inputs of all the FFs.
3) Determine which FFs will be in the HIGH state at a count X; then connect the
normal outputs of these FFs to the NAND gate inputs.
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
10
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
11
 MOD-14 ripple counter
1) Design and plot a two-bit parallel adder circuit using full adders and registers
with D FFs.
2) Design and plot the logic circuit and state transition diagram of a counter from 1
to 5.
RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN
6.9 Arithmetic Circuits
Mgtr. José A. Rumipamba López
12

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8 counters and registers

  • 1. Subject: Digital Electronics Mgtr: José A. Rumipamba López RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 1
  • 2. 2
  • 3.  Is generally equal to the number of states that the counter goes through in each complete cycle before it recycles back to its starting state. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 3 N is the number of FFs
  • 4.  In any counter, the signal at the output of the last FF (i.e., the MSB) will have a frequency equal to the input clock frequency divided by the MOD number of the counter. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 4 For example, in a MOD-16 counter, the output from the last FF will have a frequency of 1/16 of the input clock frequency
  • 5. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 5
  • 6. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 6
  • 7. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 7
  • 8. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 8
  • 9. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 9
  • 10.  To construct a counter that starts counting from all 0s and has a MOD number of X: 1) Find the smallest number of FFs such that 𝟐 𝑵 ≥ 𝑿, and connect them as a counter. 2) Connect a NAND gate to the asynchronous CLEAR inputs of all the FFs. 3) Determine which FFs will be in the HIGH state at a count X; then connect the normal outputs of these FFs to the NAND gate inputs. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 10
  • 11. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 11  MOD-14 ripple counter
  • 12. 1) Design and plot a two-bit parallel adder circuit using full adders and registers with D FFs. 2) Design and plot the logic circuit and state transition diagram of a counter from 1 to 5. RONNAL TOCCI - DIGITAL SYSTEMS, 10ª EDICIÓN 6.9 Arithmetic Circuits Mgtr. José A. Rumipamba López 12