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Title
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Date: 1/17/2020 Sheet of
File: C:D_DatacvRiscV_HPC1_TOC.SchDoc Drawn By:
TABLE OF CONTENTS
I2C SLAVE ADDRESSES
1000000_R/W ---> FPGA PRIMARYI2C (CONFIGURATION & USER)
1000001_R/W ---> 12V _A to 3V3 LTM4676A
1000010_R/W ---> 12V _B to 3V3 LTM4676A
1101001_R/W ---> RTC MAX31342 thru PCIE BUS SWITCH #4 PORT 7
1001110_R/W ---> TEMP SENSOR #1 MAX6654
1001111_R/W ---> TEMP SENSOR #2 MAX7500
TO BE SET_R/W ---> FPGA SECONDARY I2C (USER)
1000011_R/W ---> LTM4686-A (3V3 TO 1V2 & 1V0)
1000100_R/W ---> LTM4686-B (3V3 TO 1V8 & 0V9)
1000101_R/W ---> LTM4686-C (3V3 TO 2V5 & XXX)
1110000_R/W ---> I2C BUS SWITCH #1
1110001_R/W ---> I2C BUS SWITCH #2
1110010_R/W ---> I2C BUS SWITCH #3
1110011_R/W ---> I2C BUS SWITCH #4
1101010_R/W ---> PCIE BUFFER #1 PCIE BUS SWITCH #3 PORT 6
1101001_R/W ---> PCIE BUFFER #2 thru PCIE BUS SWITCH #3 PORT 7
1101010_R/W ---> PCIE BUFFER #3 PCIE BUS SWITCH #4 PORT 6
XXXXXXX_R/W ---> SOC (MASTER)
XXXXXXX_R/W ---> PCIE SW
BOARDVOLTAGES
57VDC POE_A (BRIDGE INPUTS)
57VDC POE_B (BRIDGE INPUTS)
12V_A
12V_B
12V
3V3_STDBY
5V0
3V3_RTC
3V3 (FULL PLANE)
2V5
1V8
1V5
1V2
1V0
0V9
0V88
0V6_VTT
3V3_PCIE[20..1]
PAGE-1 TOC
PAGE-2 PATENT INFO
PAGE-3 BLOCKDIAGRAM
PAGE-4 POWER SUPPLYTOPOLOGY
PAGE-5 POE SUPPLY-A
PAGE-6 POE SUPPLY-B
PAGE-7 RTC & SCAP CHARGER
PAGE-8 3V3_STDBY & 1V8_STBY & 5V0
PAGE-9 12V_ATO 3V3 SUPPLY
PAGE-10 12V_B TO 3V3 SUPPLY
PAGE-11 1V2 DDR4 & 1V0 SOC CORE SUPPLY
PAGE-12 0V9 PCIE SWITCH SUPPLY (POPULATED)
PAGE-13 0V9 PCIE SWITCH SUPPLY (OPTIONALUNPOPULATED)
PAGE-14 2V5 & 1V8 SUPPLY
PAGE-15 PCIE CONNECTOR LOAD SWITCHES #1-9
PAGE-16 PCIE CONNECTOR LOAD SWITCHES #10-18
PAGE-17 PCIE CONNECTOR LOAD SWITCHES #19&20 & FANLOAD SWITCHES
PAGE-18 I2C BUS SWITCHES
PAGE-19 PCIE CLOCKS
PAGE-20 LEVEL SHIFTER BUFFERS
PAGE-21 FTDI USB DEBUG
PAGE-22 SCREWHOLES
PAGE-23 CONTROL FPGA CORE POWER & BANK 5
PAGE-24 CONTROL FPGA BANK 3 & BANK 4
PAGE-25 CONTROL FPGA BANK 1 & BANK 2
PAGE-26 CONTROL FPGA BANK 0
PAGE-27 1V5 10G PHYADDDL SUPPLY
PAGE-28 0V88 10G PHY CORE SUPPLY
PAGE-29 10G ETHERNET PHY1 WITHIEEE1588
PAGE-30 10G ETHERNET PHY2
PAGE-31 Gb ETHERNET PHY
PAGE-33 PCIE M.2 CONNECTORS 4&5&6&7
PAGE-34 PCIE M.2 CONNECTORS 8&9&10&11
PAGE-36 PCIE M.2 CONNECTORS 16&17&18&19
PAGE-37 FRONT PANEL LEDS & BUTTONS
PAGE-32 PCIE M.2 CONNECTORS 1&2&3&20
FAN1_VCC
FAN2_VCC
FAN3_VCC
FAN4_VCC
POWER UP SEQUENCE PER DEVICE
POLARFIRE FPGA: VDDIO --> VDDCORE --> VDDAUXVDDAUX (Auxiliary for GPIO)/VDD18 . Power-up ramp times must be less than 50ms.
SWITCHTEC PCIE SWITCH: 3V3 --> 0V9 CORE --> 1V8 I/O
DDR4: 2V5 (VPP) --> 1V2 DDR4 --> 0V6 Vtt
POWER UP SEQUENCE FOR BOARD
3V3_STBY / 3V3_RTC / 5V0 / --> 3V3 --> 2V5/1V8 -------------
BOARDGROUNDS
GND
GND_CHASSIS
SPECIAL NOTES
The plane underneath the pads of DC blockingcapacitors (0.1uF 0402 on differential lines) should be removed.
SILK SCREENINDICATOR : CHARACTERS INSIDE ARE SILK SCREEN
<SIGNALNAME>_P / <SIGNALNAME>_NDEPICTS DIFFERENTIAL PAIR.
ALL RESISTORS HAVE 1%TOLERANCE !
PAGE-35 PCIE M.2 CONNECTORS 12&13&14&15
1011110_R/W ---> TDP158 HDMI REDRIVER
0000001_R/W ---> REDRIVER #1
0000010_R/W ---> REDRIVER #2
1V8_STDBY
PRELIMINARY
DESIGNED BY ALİ UZEL. CONFIDENTIAL.
TABLE OF CONTENTS.
BREAK SOLDER PASTE INTO SMALLER PIECES FOR EXPOSED PADS !!
2V5 must be stable before 1V2 DDR4, 1V8 must be stable before 1V1 LPDDR4
50ms MAX. ramp-up time for SOC voltages !!
Board FOSOH-V -- PRELIMINARY
TM
PAGE-38 12V_A& 12V_B POWER INPUTS
PAGE-39 FRONT PANEL: 1G ETHERNET RJ45 & OCULINK
PAGE-40 FRONT PANEL: 10G/1G SFP/SFP+ CONNECTORS
PAGE-41 FRONT PANEL: 1G/10G ETHERNET RJ45
PAGE-42 POWER LOSS PROTECTION (PLP) SUPERCAP CHARGER
PAGE-43 FAST POWER DOWNDISCHARGE
PAGE-44 HDMI 2.0
PAGE-45 PCIE 3.0 SWITCH POWER PINS
PAGE-46 PCIE 3.0 SWITCH STACKS
PAGE-47 PCIE 3.0 SWITCH SPI & BOOTSTRAP & GPIO
PAGE-48 DDR4-1600 SOC FABRIC MEMORY
PAGE-49 LPDDR4-1600 SOC MSS MEMORY
PAGE-50 USB3.1 CONNECTORS FOR SERIAL TILELINK
PAGE-51 SOC JTAG& QSPI & SDINTERFACES
PAGE-52 SOC POWER PINS
PAGE-53 SOC TRANSCEIVER INTERFACE
PAGE-54 SOC LPDDR4-1600 INTERFACE
PAGE-55 SOC DDR4-1600 INTERFACE
PAGE-56 SOC HSIO (LVDS) FOR PCIE CONNECTORS
PAGE-57 SOC MSS GPIO PINS & THERM SENSOR
PAGE-58 LPDDR4 SUPPLY
PAGE-59 PCIE - I2C EXPANSION FPGA (EXPFPGA)
PAGE-60 SOC REFERENCE CLOCKS
PAGE-63 REVISIONHISTORY
PATENTED BY Ali UZEL
PAGE-61 BLANK PAGE-1
PAGE-62 BLANK PAGE-2
1V1
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Title
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Date: 1/17/2020 Sheet of
File: C:D_Data..2_PATENT INFO.SchDoc Drawn By:
PRELIMINARY
PRELIMINARY SCHEMATIC
RISC-V based Flexible Open SOurce Hardware
DESIGNED BY Ali UZEL / CONFIDENTIAL
Board FOSOH-V
TM
board FOSOH-V
FSHV-00-01102020 Ver 0.0
Designed by Ali UZEL
TM
PATENT INFO
PATENT PENDING
Patent pending
PATENTED BY Ali UZEL
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Date: 1/17/2020 Sheet of
File: C:D_Data..3_BLOCK DIAGRAM.SchDocDrawn By:
PRELIMINARY
FOSOH-V BLOCK DIAGRAM
PCIE SW x48
SOC
CONTROL FPGA
10G PHY
10G PHY
1G PHY
RJ45
RJ45
RJ45
x4 PCIE 2.0
SGMII / 1G
XCVR / 10G / x1
XCVR / 10G / x1
SFP+ CON.
XCVR / 10G / x1
SFP+ CON.
XCVR / 10G / x1
POE-A
POE-B
12V/3V3
12V/3V3
12V_A
12V_B
3V3
DC/DC REGS.
STDBY & SCAP REGS.
PCIE M.2
PCIE M.2
x 20 M.2 CONN.
x2 PCIE 3.0
x2 PCIE 3.0
OCULINK CONN.x4 PCIE 3.0
USB 3.1
USB 3.1
HDMI
x2 LVDS
x2 LVDS
BOARD CONTROL
XCVR / HDMI 2.0 / x4
DRIVERS
DRIVER
XCVR / x2
XCVR / x2
12V JACK
12V JACK
LEDS
CLOCKS
DIP SW.
LPDDR4
DDR4
DDR4
FLASH
FLASH
MINI USB FTDI
USB 2.0 UART
TEST CONN.
SD CONN. SD CNTRL.
PCI-I2C EXP.
FPGA
I2C
PCIE CTRL
PCIE M.2
IEEE 1588
x 20 M.2 CONN. FOR SSD/COMPUTING
PATENTED BY Ali UZEL
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Date: 1/17/2020 Sheet of
File: C:D_Data..4_POWER SUPPLY TOPOLOGY.SchDocDrawn By:
POWER SUPPLY TOPOLOGY
POE SUPPLY-A
POE SUPPLY-B
LTM4676A
LTM4676A
12V_A
12V_B
3V3 PLANE (CURRENT SHARED) - 52A MAX.
LTM4686-1 LTM4686-1
1V8
2V5
LTM4686-1
0V9
TPS51200
DDR4_1V2
VTT_0V6
SCHOTTKY
SINGLE CHANNEL
LTC335512V
SUPER CAP
3V3_RTC
LTM4622A
1V8_STDBY 3V3_STDBY
LDO
I2C
LT3070-1
LDO
LT3070-1
LDO
0V88
LT3070-1
LDO
1V5
12V_ADAPTER_B
12V_ADAPTER_A
I2C HEADER
CPU
HEADERS FOR
ENABLE LTM4676A & LTM4686-1
AUX
PRELIMINARY
BQ24640
4.7 uF
SUPER CAPS
2 x 90 uF
12V_A 12V_B
LT3070-1
LDO
1V1
LTM4686-1
DNM
0V88
1V05
SCHOTTKY
LM340
LDO
5V0
PATENTED BY Ali UZEL