2. EE6602 – EMBEDDED SYSTEM
OBJECTIVES:
To introduce the Building Blocks of Embedded System
To Educate in Various Embedded Development Strategies
To Introduce Bus Communication in processors, Input/output interfacing.
To impart knowledge in Various processor scheduling algorithms.
To introduce Basics of Real time operating system and example tutorials to discuss
on one real-time operating system tool
1
3. EE6602 – EMBEDDED SYSTEM
Syllabus:
UNIT I
INTRODUCTION TO EMBEDDED SYSTEMS
Introduction to Embedded Systems – The build process for embedded systems-
Structural units in Embedded processor , selection of processor & memory devices- DMA
– Memory management methods- Timer and Counting devices, Watchdog Timer, Real
Time Clock, In circuit emulator, Target Hardware Debugging.
UNIT II
EMBEDDED NETWORKING
Embedded Networking: Introduction, I/O Device Ports & Buses– Serial Bus
communication protocols -RS232 standard – RS422 – RS485 - CAN Bus -Serial
Peripheral Interface (SPI) – Inter Integrated Circuits (I2C) –need for device drivers.
2
4. EE6602 – EMBEDDED SYSTEM
Syllabus:
UNIT III
EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT
Embedded Product Development Life Cycle- objectives, different phases of EDLC, Modelling
of EDLC; issues in Hardware-software Co-design, Data Flow Graph, state machine model,
Sequential Program Model, concurrent Model, object oriented Model.
UNIT IV
RTOS BASED EMBEDDED SYSTEM DESIGN
Introduction to basic concepts of RTOS- Task, process & threads, interrupt routines in RTOS,
Multiprocessing and Multitasking, Preemptive and non-reemptive scheduling, Task
communication-shared memory, message passing-, Inter process Communication –
synchronization between processes-semaphores, Mailbox, pipes, priority inversion, priority
inheritance, comparison of Real time Operating systems: Vx Works, чC/OS-II, RT Linux.
UNIT V
EMBEDDED SYSTEM APPLICATION DEVELOPMENT
Case Study of Washing Machine- Automotive Application- Smart card System Application.
3
5. TOPICS TO BE DISCUSSED
• System
• Embedded System
• Components
• Classifications
• Processors
• Other Hardware
• Software
• Applications
6. 5
What is a system?
A system is a way of working,
organizing or doing one or many tasks
according to a fixed plan, program or
set of rules.
A system is also an arrangement
in which all its units assemble and
work together according to the plan or
program.
7. 6
WATCH
It is a time display SYSTEM
Parts: Hardware, Needles, Battery, Dial,
Chassis and Strap
Rules
1.All needles move clockwise only
2.A thin needle rotates every second
3.A long needle rotates every minute
4.A short needle rotates every hour
5.All needles return to the original position after 12 hours
8. 7
WASHING MACHINE
It is an automatic clothes washing SYSTEM
Parts: Status display panel, Switches & Dials, Motor,
Power supply & control unit, Inner water level sensor and
solenoid valve.
Rules
1.Wash by spinning
2.Rinse
3.Drying
4.Wash over by blinking
5.Each step display the process stage
6.In case interruption, execute only the remaining
9. 8
Definition: An Embedded System is one that has
computer hardware with software embedded in it as
one of its important components.
SOFTWARE PROGRAM
#include <16f876a.h>
#use delay (clock=20000000)
#byte PORTB=6
main()
{
set_tris_b(0);
portb=255; //decimal
delay_ms(1000);
portb=0x55; //hexadecimal
delay_ms(1000);
portb=0b10101010; //binary
delay_ms(500);
}
Its software embeds in
ROM (Read Only
Memory). It does not need
secondary memories as in
a computer
HARDWARE
10. 9
A Microprocessor
A Large Memory
(Primary and Secondary)
(RAM, ROM and caches)
Input Units
(Keyboard, Mouse, Scanner, etc.)
Output Units
(Monitor, printer, etc.)
Networking Units
(Ethernet Card, Drivers, etc.)
I/O Units
(Modem, Fax cum Modem, etc.)
11. 10
• It has Hardware
Processor, Timers, Interrupt controller, I/O Devices, Memories, Ports,
etc.
• It has main Application Software
Which may perform concurrently the series of tasks or multiple tasks.
• It has Real Time Operating System (RTOS)
RTOS defines the way the system work. Which supervise the application
software. It sets the rules during the execution of the application
program. A small scale embedded system may not need an RTOS.
13. 12
An embedded system is software designed to keep
in view three constraints:
– Available system memory
– Available processor speed
– The need to limit the power dissipation
When running the system continuously in cycles of wait for
events, run, stop and wakeup.
14. 13
1.Pragram is Preloaded or embedded in the ROM
2.The system functions in real time. The task
execute according to priorities.
3.Dedicated set of function
4.Complex algorithm
16. 15
1. Small Scale Embedded System
2. Medium Scale Embedded System
3. Sophisticated Embedded System
17. 16
• Single 8 bit or 16bit Microcontroller.
• Little hardware and software complexity.
• They May even be battery operated.
• Usually “C” is used for developing these system.
• The need to limit power dissipation when system is running
continuously.
Programming tools:
Editor, Assembler and Cross Assembler
18. 17
• Single or few 16 or 32 bit microcontrollers or Digital
Signal Processors (DSP) or Reduced Instructions
Set Computers (RISC).
• Both hardware and software complexity.
Programming tools:
RTOS, Source code Engineering Tool,
Simulator, Debugger and Integrated Development
Environment (IDE).
19. 18
• Enormous hardware and software complexity
• Which may need scalable processor or configurable processor
and programming logic arrays.
• Constrained by the processing speed available in their
hardware units.
Programming Tools:
For these systems may not be readily available at a
reasonable cost or may not be available at all. A compiler or
retargetable compiler might have to br developed for this.
20. 19
• A Processor is the heart of the Embedded
System.
• For an embedded system designer
knowledge of microprocessor and
microcontroller is a must.
Two Essential Units: Operations
Control Unit (CU), Fetch
Execution Unit (EU) Execute
21. 20
1. General Purpose processor (GPP)
Microprocessor
Microcontroller
Embedded Processor
Digital signal Processor
2. Application Specific System Processor
(ASSP)
3. Multi Processor System using GPPs
22. 21
• A microprocessor is a single chip semi conductor
device also which is a computer on chip, but not a
complete computer.
• Its CPU contains an ALU, a program counter, a stack
pointer, some working register, a clock timing circuit
and interrupt circuit on a single chip.
• To make complete micro computer, one must add
memory usually ROM and RAM, memory decoder, an
oscillator and a number of serial and parallel ports.
23. 22
1st Generation (4 bit processors)
4004 and 4040 4 bit in early 1970 by Intel (Integrated Electronics)
2nd Generation (8 bit processors)
8008 and 8080 8 bit in 1974 Intel with +5 V Input supply 8080 8085 8 bit
3rd Generation (16 bit processors)
8086 16 bit. Same as 8086, the 8088 introduced 8088 has only 8 bit data bus
(This made it easier to interface to the common 8 bit peripheral devices
available at the time)
Followed by:
The 80186 & 80286 (16 bit processor), the 80386 & 80486 (a 32 bit processor),
leading to the Pentium range of microprocessors (64 bit processors)
available today. The 80x86 and Pentium processors have all been designed
for use in personal computer type applications and have large memory maps.
25. 24
• A microcontroller is a functional
computer system-on-a-chip. It contains a
processor, memory, and programmable
input/output peripherals.
• Microcontrollers include an integrated
CPU, memory (a small amount of RAM,
program memory, or both) and peripherals
capable of input and output.
27. 26
MICROPROCESSOR MICROCONTROLLER
The functional blocks are ALU,
registers, timing & control units
It includes functional blocks of
microprocessors & in addition has
timer, parallel i/o, RAM, EPROM,
ADC & DAC
Bit handling instruction is less, One
or two type only
Many type of bit handling
instruction
Rapid movements of code and
data between external memory & MP
Rapid movements of code and
data within MC
It is used for designing general
purpose digital computers system
They are used for designing
application specific dedicated
systems
28. 27
• Special microprocessors & microcontrollers
often called, Embedded processors.
• An embedded processor is used when fast
processing fast context-switching & atomic
ALU operations are needed.
Examples : ARM 7, INTEL i960, AMD 29050.
30. 29
• ASSP is dedicated to specific tasks and
provides a faster solution.
• An ASSP is used as an additional processing
unit for running the application in place of
using embedded software.
Examples : IIM7100, W3100A
31. 30
• Multiple processors are used when a
single processor does not meet the
needs of different task.
• The operations of all the processors
are synchronized to obtain an optimum
performance.
32. 31
• Power Source
• Clock Oscillator
• Real Time Clock (RTC)
• Reset Circuit, Power-up Reset and watchdog timer Reset
• Memory
• I/O Ports, I/O Buses
• Interrupt Handler
• DAC and ADC
• LCD and LED Display
• Keypad/Keyboard
38. I/O Types and Examples
Port: A port at a device can transmit (send) or
receive through wire or wireless.
Input port: Input port means a circuit to where
bit or bits can be input (received) from an
external device, peripheral or system.
Output port: Output port means a circuit from
where bit or bits can be output (sent) to an
external device, peripheral or system.
40. • Serial means in series of successive instants.
• Parallel means at the same instance.
• Serial
• Parallel
Serial
input
Serial
output
Parallel
input
Parallel
output
43. EXAMPLES
• Examples of synchronous serial-
communication devices are
- SPI and high-level data link control
• Examples of asynchronous serial-
communication devices are
- RS232C and UART
46. Serial Communication Devices
• Serial Communication devices use one of
three modes of communication for
transmitting data frames
1) Serial synchronous 2) Isosynchronous 3)
Asynchronous
47. TEN WAYS OF SYNCHRONIZATION
Ten ways by which the synchronous signals with the clocking information transmit
from a master device to slave device
50. HDLC Protocol
• HDLC (High-level Data Link Control) is an
international Standard Synchronous serial
communication protocol for a data-link
network. The data, link from point to pint and
between multiple points using HDLC. HDLC is
for physical devices on a telecommunication
and computer network.
• The two formats of HDLC specifications are
standard and extended formats.
55. System buses are shared between the controllers and
an I/O processor and multiple controllers that have to
access the bus, but only one of them can be granted
the bus mater status at any one instance
59. BUS
The name stands for “Inter - Integrated Circuit Bus”
A Small Area Network connecting ICs and other
electronic systems
Originally intended for operation on one
single board / PCB
Synchronous Serial Signal
Two wires carry information between
a number of devices
One wire use for the data
One wire used for the clock
Today, a variety of devices are available with I2C
Interfaces
Microcontroller, EEPROM, Real-Timer, interface chips, LCD
driver, A/D converter
60. Interconnecting number of device circuits
• Assume flash memory, touch screen, ICs for
measuring temperatures and ICs for
measuring pressures at a number of processes
in a plant.
• ICs mutually network through a common
synchronous serial bus I 2C
• An 'Inter Integrated Circuit' (I2C) bus, a
popular bus for these circuits.
61. Synchronous Serial Bus Communication for
networking
• Each specific I/O synchronous serial device
may be connected to other using specific
interfaces, for example, with I/O device using
I 2C controller
• I 2C Bus communication − use of only
simplifies the number of connections and
provides a common way (protocol) of
connecting different or same type of I/O
devices using synchronous serial
communication
62. • Originally developed at Philips Originally
developed at Philips Semiconductors
• Synchronous Serial Communication 400 kbps
up to 2 m and 100 kbps for longer distances
• Three I 2C standards
- Industrial 100 kbps I 2C
- 100 kbps SM I2C
- 400 kbps I 2 C
63. I2C Bus using C Bus using serial data
line and clock
64. I 2C Bus
• The Bus has two lines that carry its signals—
one line is for the clock and one is for bi-
directional data.
• There is a standard protocol for the I 2C bus.
65. Device Addresses and Master in the
I2C bus
• Each device has a 7-bit address using which
the data transfers take place.
• Master can address 127 other slaves at an
instance.
• Master has at a processing element
functioning as bus controller or a
microcontroller with I 2C (Inter Integrated
Circuit) bus interface circuit.
66. Slaves and Masters in the I2C bus
• Each slave can also optionally has I 2C (Inter
Integrated Circuit) bus controller and
processing element.
• Number of masters can be connected on the
bus.
• However, at an instance, master is one, which
initiates a data transfer on SDA (serial data)
line and which transmits the SCL (serial clock)
pulses. From master, a data frame has fields
beginning from start bit
68. Synchronous Serial Bus Fields and its
length
• First field of 1 bit─ Start bit similar to one in an UART
• Second field of 7 bits ─ address field. It defines the
slave address, which is being sent the data frame (of
many bytes) by the master
• Third field of 1 control bit─ defines whether a read or
write cycle is in progress
• Fourth field of 1 control bit─ defines whether is the
present data is an acknowledgment (from slave)
69. Synchronous Serial Bus Fields and its
length
• Fifth field of 8 bits ─ I 2C device data byte
• Sixth field of 1-bit─ bit NACK (negative
acknowledgement) from the receiver. If active
then acknowledgment after a transfer is not
needed from the slave, else acknowledgement
is expected from the slave
• Seventh field of 1 bit ─ stop bit like in an UART
70. Disadvantage of I 2C bus
• Time taken by algorithm in the hardware that
analyzes the bits through I 2C in case the slave
hardware does not provide for the hardware
that supports it.
• Certain ICs support the protocol and certain
do not.
• Open collector drivers at the master need a
pull-up resistance of 2.2 K on each line
71. I2C Hardware Details
Devices connected to the bus must have an open
drain or open collector output for serial clock and
data signal
The device must also be able to sense the logic level
on these pins
All devices have a common ground reference
The serial clock and data lines are connected to
Vdd(typically +5V) through pull up resistors
At any given moment the I2C bus is:
Quiescent (Idle), or
in Master transmit mode or
in Master receive mode.
72. I2C Electrical Aspects
• If any single node writes a zero, the entire line is zero
•I2C devices are wire ANDed together.
73. Bit Transfer on the I2C Bus
In normal data transfer, the data line only changes state
when the clock is low
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
74. Start and Stop Conditions
A transition of the data line while the clock line is high is
defined as either a start or a stop condition.
Both start and stop conditions are generated by the bus
master
The bus is considered busy after a start condition, until a
stop condition occurs
Start
Condition
Stop
Condition
SCL SCL
SDASDA
76. 1. CANBUS Introduction
What is CANBUS?
Who uses CANBUS?
CANBUS history
CANBUS timeline
2. CANBUS Characteristics
OSI Model
Physical Layer
Transmission Characteristics
3. Message Oriented Communication
4. Message Format
5. Bus Arbitration
Presentation Goals
40
77. CANBUS or CAN bus – Controller Area Network bus
An automotive serial bus system developed to satisfy
the following requirements:
Network multiple microcontrollers with 1 pair of wires.
Allow microcontrollers communicate with each other.
High speed, real-time communication.
Provide noise immunity in an electrically noisy environment.
Low cost
What is CANBUS?
41
78. • Designed specifically for automotive applications
• Today - industrial automation / medical equipment
Who uses CANBUS?
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Automotive Medical / Industrial
Markets
CANBUS Market Distribution
42
81. • CAN is a closed network
– – no need for security, sessions or logins.
– - no user interface requirements.
• Physical and Data Link layers in silicon.
CANBUS and the OSI Model
45
82. CANBUS Physical Layer
CAN bus network
Physical medium – two wires terminated at both ends by resistors.
Differential signal - better noise immunity.
Benefits:
Reduced weight, Reduced cost
Fewer wires = Increased reliability
vs.
http://canbuskit.com/what.php
46
89. • CAN bus – Controller Area Network bus
• Primarily used for building ECU networks in
automotive applications.
• Two wires
• OSI - Physical and Data link layers
• Differential signal - noise immunity
• 1Mbit/s, 120’
• Messages contain up to 8 bytes of data
Summary
53
90. A “0” (low voltage) on the bus by 1 node wins over a
“1” (high voltage) on the bus.
Bus arbitration
54
96. What is EDLC?
• Embedded Product Development Life Cycle is an
‘Analysis-Design-Implementation’ based standard
problem solving approach for Embedded Product
Development.
• In any product development application, the first
and foremost step is to figure out what product
needs to be developed (analysis), next you need
to figure out a good approach fro building it
(design) and last but not least you need to
develop it (implementation).
97. Why EDLC?
• EDLC is essential for understanding the scope and
complexity of the work involved in any embedded product
development.
• EDLC defines the interaction and activities among various
groups of a product development sector including project
management, system design and development (hardware,
firmware and enclosure design and development), system
testing, release management and quality assurance.
• The standards imposed by EDLC on a product development
makes the product, developer independent in terms of
standard documents and it also provides uniformity in
development approaches.
98. OBJECTIVES OF EDLC
• EDLC has three primary objectives, namely
- Ensure that high quality products are
delivered to end user.
- Risk minimisation and defect prevention in
product development through project
management.
- Maximise the productivity.
99. DIFFERENT PHASES OF EDLC
• A typical simple product contains five minimal
phases namely,
- Requirement Analysis
- Development
- Testing
- Deployment
- Maintenance
100. DIFFERENT PHASES OF EDLC
Where as classic embedded life cycle model contains the
following phases:
1. Need
2. Conceptualization
3. Analysis
4. Design
5. Development and Testing
6. Deployment
7. Support
8. Upgrades
9. Retirement/Disposal
102. NEED
• Any Embedded product evolves as an output
of a need. The need may come from an
individual or from the public or from a
company or from an end user/client.
• Need should be articulated to initiate the
Product Development Life Cycle and based on
the need for the product, a statement of need
or concept proposal is prepared.
103. CONCEPT PROPOSAL
• The concept proposal must be reviewed by the
senior management and funding agency and
should get necessary approval.
• Once the proposal gets approval, it goes to a
product development team.
• The product development need can be visualized
in any one of the following three needs:
1. New or Custom Product Development
2. Product Re-engineering
3. Product Maintenance
104. CONCEPTUALISATION
• Conceptualization is the product concept
development phase and it begins immediately
after a concept proposal is formally approved.
• Conceptualization phase defines the scope of
the concept, performs cost benefit analysis
and feasibility study and prepares project
management and risk management plans.
106. CONCEPTUALISATION
• The conceptualization phase involves two types of
activities:
1. Planning activity
2. Analysis and study activity
- Feasibility Study
- Cost Benefit Analysis (CBA)
- Common unit of Measurement
- Market Choice based benefit measurement
- Targeted end users
- Product Scope
- Planning Activities
- Resource Planning
- Risk Management Plans
108. Analysis and Documentation
• The various requirements that need to be addressed during
the requirement analysis phase for a product under
consideration are listed below:
1. Functional capabilities like performance, operational
characteristics
2. Operational and non-operational quality attributes
3. Product external interface requirement
4. Data requirements
5. User manuals
6. Operational requirements
7. Maintenance requirements
8. General assumptions
112. DEVELOPMENT AND TESTING
• The development activities can be partitioned
into:
1. Embedded Hardware Development
2. Embedded Firmware Development
3. Product Enclosure Development
113. Embedded Firmware Development
• The testing phase can be divided into
1. Unit Testing
2. Integration Testing
3. System Testing
4. User Acceptance Testing
114. DEPLOYMENT
• The important tasks performed during the
deployment phase are:
1. Notification of product deployment
2. Execution of training plan
3. Product installation
4. Product post implementation review
115. SUPPORT
• The various activities involved in the support
phase are:
1. Setup dedicated support wing
2. Identify bugs and areas of improvement
117. RETIREMENT/DISPOSAL
• The disposition of a product is essential due to
the following reasons:
1. Rapid technology advancement
2. Increased user needs
118. EDLC APPROACHES
(MODELING THE EDLC)
• The term ‘Modelling’ in Embedded Product
Development Life Cycle refers to the
interconnection of various phases involved in the
development of an embedded product.
• The various approaches adopted or models used
in Modelling EDLC are described below:
1. Linear or Waterfall Model
2. Iterative/Incremental or Fountain Model
3. Prototyping/Evolutionary Model
4. Spiral Model
123. Hardware-Software Co-design
• Issues in Hardware Software Co-Design
- Selecting the model
- Selecting the Architecture
- Controller Architecture
- Datapath Architecture
- Finite state machine Datapath (FSMD)
- Complex Instruction Set Computing (CISC)
- Reduced Instruction Set Computing (RISC)
- Very Long Instruction Word (VLIW)
- Parallel Processing Architecture-Example 1) Single Instruction
Multiple Data (SIMD) 2) Multiple Instruction Multiple Data (MIMD)
- Selecting the Language
- Partitioning System Requirements into Hardware and Software
124. Computational Models in Embedded
Design
The following computational models are used in
embedded system design.
- Data flow graph model
- State machine model
- Sequential program model
- Concurrent process model
- Object oriented model
131. Sequential Program Model For Seat
Machine Warning System
The execution of functions in a sequential
program model for the ‘Seat Belt Warning’ system
132. Sequential Program Model For Seat
Machine Warning System
Flowchart approach for
modelling the ‘Seat Belt
Warning’ system
explained in the FSM
modelling section
138. Features
Certifiable for use in safety critical systems
99% compliant with the Motor Industry Software Reliability
Association (MISRA) C coding standards
Small footprint
Large user base
Complete with all source code.
No royalties
139. Description
µC/OS-II, The Real-Time Kernel, is a
Highly portable,
ROMable,
Very Scalable,
Preemptive real-time Multitasking kernel RTOS for microprocessors and microcontrollers.
µC/OS-II is provided with all source code, which is 100 percent
portable ANSI C.
Easily scaled because of the modular nature of the source code,
µC/OS-II can present a very small footprint for space-constrained
embedded designs.
140. µC/OS-II has been widely embraced and can be delivered as a pre-
certifiable software component for safety-critical systems. Including
following Fields:
Avionics RTCA DO-178B
EUROCAE ED-12B
Medical FDA 510(k)
Transportation
Nuclear Systems Standard IEC 61058
DO-178B Level A Class III Medical Devices
SIL3/SIL4 ICE-Certified Systems.
141. Micrium's uC/OS-II can manage up to 255 tasks and provides the
following services:
Semaphores
Event flags
Mutual exclusion semaphores (to reduce priority inversions)
Message mailboxes
Message queues
Task management (create, delete, change priority,
suspend/resume, etc.)
Fixed sized memory block management
Time management
Timer management
143. Task Management
Task Feature
Task Creation
Task Stack & Stack Checking
Task Deletion
Change a Task’s Priority
Suspend and Resume a Task
Get Information about a Task
145. Task Feature
μC / OS-II can manage up to 64 tasks.
The four highest priority tasks and the four lowest priority tasks are
reserved for its own use. This leaves us with 56 application tasks.
The lower value of the priority, the higher priority of the task.
The task priority number also serves as the task identifier
A task, also called a thread, is a simple program that thinks it has the
CPU all to itself.
Each task is assigned a priority, its own set of CPU registers, and its
own stack area.
147. Task Creation
Creating an RT task, it has to get the memory without delay: This is
difficult because memory has to be allocated and a lot of data
structures, code segment must be copied/initialized.
Two Functions for Creating a Task:
OSTaskCreate()
OSTaskCreateExt()
149. Task Stack & Stack Checking
To create a task we have to allocate some stack in the memory.
The stack will be allocated into the memory of the processor.
After the task is created, the task has to get a stack in which it will
store its data
A stack must consist of contiguous memory locations
It is necessary to determine how much stack space a task actually
uses.
150. Task Deletion
Deleting a task means the task will be returned to its dormant
state and does not mean that the code for the task will be deleted.
The calling task can delete itself.
If another task tries to delete the current task, the resources are
not freed and thus are lost. So the task has to delete itself after it
uses its resources.
151. Task Management
Priority of the calling task or another task can be changed at run
time.
A task can suspend itself or another task, a suspended task can
resume itself.
A task can obtain information about itself or other tasks.
This information can be used to know what the task is doing at a
particular time.
152. Kernel:
The kernel is the part of a multitasking system responsible for the
Management of tasks (that is, for managing the CPU's time) and
Communication between tasks.
When the kernel decides to run a different task, it simply saves the
current task's context (CPU registers) onto the current task's stack,
each task is assigned its own stack area in memory.
Once this operation is performed, the new task's context is restored
from its stack area and then, execution of the new task's code is
resumed.
This process is called a context switch or a task switch.
The use of a real-time kernel will generally simplify the design of
systems by allowing the application to be divided into multiple tasks
managed by the kernel.
153. A kernel will add overhead to your system because it requires extra ROM
(code space), additional RAM for the kernel data structures but most
importantly, each task requires its own stack space which has a tendency to
eat up RAM quite quickly.
A kernel will also consume CPU time (typically between 2 and 5%).
Single chip microcontrollers are generally not able to run a real-time kernel
because they have very little RAM.
A kernel can allow you to make better use of your CPU by providing you
with indispensable services such as semaphore management, mailboxes,
queues, time delays, etc.
Once you design a system using a real-time kernel, you will not want to go
back to a foreground/background system.
154. Context Switching or Task Switching:
When a multitasking kernel decides to run a different task, it
simply saves the current task's context (CPU registers) in the
current task's context storage area – it’s stack.
Once this operation is performed, the new task's context is
restored from its storage area and then resumes execution of the
new task's code.
This process is called a context switch or a task switch.
Context switching adds overhead to the application.
The more registers a CPU has, the higher the overhead.
The time required to perform a context switch is determined by
how many registers have to be saved and restored by the CPU.
Performance of a real-time kernel should not be judged on how
many context switches the kernel is capable of doing per second.
155. TASK #1
Stack StackStack
TASK #nTASK #2
CPU Registers
Memory
CPU
Task Control Block Task Control Block Task Control BlockStatus
SP
Priority
Status
SP
Priority
Status
SP
Priority
SP
Context
157. Time Management
Clock Tick: A clock tick is a periodic time source to keep track
of time delays and time outs.
Tick intervals: 10 ~ 100 ms.
The faster tick rate, the higher overhead imposed on the
system.
When ever a clock tick occurs μC/OS-II increments a 32-bit
counter
The counter starts at zero, and rolls over to 4,294,967,295
(2^32-1) ticks.
A task can be delayed and a delayed task can also be resumed
158. OSTimeDlyHMSM(): hours(H), minutes(M), seconds(S),
milliseconds(m)
Maximum Delay 256 hours (11days)
Example: OSTimeDlyHMSM( 0, 0, 1, 500);
OSTimeDlyResume(): Resuming a Delayed Task
System Time, OSTimeGet() and OSTimeSet(): 32-bit counter
160. Memory Management
Fixed-sized memory blocks from a partition made of a contiguous
memory area.
All memory blocks are the same size and the partition contains an
integral number of blocks.
Allocation and deallocation of these memory blocks is done in
constant time and is deterministic.
Each memory partition consists of several fixed-sized memory blocks.
A task obtains memory blocks from the memory partition.
A task must create a memory partition before it can be used.
Multiple memory partitions can exist, so a task can obtain memory
blocks of different sizes
A specific memory block should be returned to its memory partition
from which it came
162. Memory Management
OSMemGet():
Get a memory block from one of the created memory partitions
OSMemPut():
Returning a Memory Block to the appropriate partition
OSMemQuery():
Obtaining status of a Memory partition
164. Inter Task Communication
It is sometimes necessary for a task or an ISR to communicate
information to another task. This information transfer is called intertask
communication.
Information may be communicated between tasks in two ways:
Through global data
By sending messages.
When using global variables, each task or ISR must ensure that it has
exclusive access to the variables.
If an ISR is involved, the only way to ensure exclusive access to the
common variables is to disable interrupts.
165. Note that a task can only communicate information to an ISR by using
global variables.
A task is not aware when a global variable is changed by an ISR unless
the ISR signals the task by using a semaphore or by having the task
regularly poll the contents of the variable.
If two tasks are sharing data each can gain exclusive access to the
variables by using either disabling/enabling interrupts or through a
semaphore.
To correct this situation, we should consider using either a Message
Mailbox or a Message Queue.
166. Inter-Task or Inter Process Communication in μC/OS takes place
using
Semaphores
Message Mailbox
Message Queues
Tasks and Interrupt service routines (ISR) can interact with each
other through an ECB (Event Control Block)
167. Single Task Waiting:
ISR TaskECB
Signal
(1)
Timeout
(3)
Wait
(2)
TaskECB
Signal
(1)
Timeout
(3)
WaitTask
(2)
A
169. Tasks can wait and signal along with an optional time out:
C
Task Wait/
Signal
Task
ECB
Timeout
Timeout
Wait/
Signal
170. Semaphore:
A semaphore is a protocol mechanism used to control access to a
shared resource (Mutual Exclusion), signal the occurrence of an
event or allow two tasks to synchronize their activities.
A semaphore is basically a key that your code acquires in order to
continue execution.
If the semaphore is already in use, the requesting task is suspended
until the semaphore is released by its current owner.
A suspended task consumes little or no CPU time.
16-bit unsigned integer used to hold the semaphore count (0 to
65535) a list of tasks waiting for the semaphore count to be greater
than 0.
171. µC/OS-II provides five services to semaphores
OSSemCreate()
OSSemPend()
OSSemPost()
OSSemAccept()
OSSemQuery()
Task
ISR
TaskOR
N
OSSemPost()
OSSemAccept()
OSSemPost()
OSSemCreate()
OSSemPend()
OSSemAccept()
OSSemQuery()
N
172. Message Mailboxes:
Messages can be sent to a task through kernel services. A
Message Mailbox also called a message exchange is typically a
pointer size variable.
Through a service provided by the kernel, a task or an ISR can
deposit a message (the pointer) into this mailbox.
Similarly, one or more tasks can receive messages through a
service provided by the kernel.
Both the sending task and receiving task will agree as to what the
pointer is actually pointing to.
A Message Mailbox is a uC/OS-II object that allows a task or an
ISR to send a pointer sized variable to another task.
173. µC/OS-II provides five services to mailboxes:
OSMboxCreate()
OSMboxPend()
OSMboxPost()
OSMboxAccept()
OSMboxQuery()
Task
Task
ISR
OSMboxPost()
OSMboxAccept()
Mail Box
Message
OSMboxPost()
OSMboxPend()
OSMboxAccept()
OSMboxQuery()
OSMboxCreate()
174. Message Queues:
A Message Queue is used to send one or more messages to a task. A
message queue is basically an Array of Mailboxes.
Through a service provided by the kernel, a task or an ISR can
deposit a message (the pointer) into a message queue.
Both the sending task and receiving task will agree as to what the
pointer is actually pointing to.
Generally the first message inserted in the queue will be the first
message extracted from the queue (FIFO).
In addition to extract messages in a FIFO fashion, μC/OS-II allows a
task to get messages Last-In-First-Out (LIFO).
175. A message queue is a µC/OS-II object that allows a task or an ISR to
send pointer sized variables to another task.
µC/OS-II provides seven services to Queues:
OSQCreate()
OSQPend()
OSQPost()
OSQPostFront()
OSQAccept()
OSQFlush()
OSQQuery()
Task
Task
ISR
N
OSQPost()
OSQPostFront()
OSQFlush()
OSQAccept()
Queue
Message
OSQPend()
OSQAccept()
OSQQuery()
OSQPost()
OSQPostFront()
OSQFlush()
OSQCreate()
178. SCHEDULING
The scheduler also called the dispatcher. It's is the part of the kernel
responsible for determining which task will run next.
Most of the real-time kernels are priority based. Each task is assigned a
priority based on its importance.
The priority for each task is application specific.
In a priority-based kernel, control of the CPU will always be given to
the highest priority task ready-to-run.
When the highest-priority task gets the CPU, however, is determined
by the type of kernel used.
There are two types of priority-based kernels: Non-Preemptive and
Preemptive.
179. Scheduler is responsible for time-sharing of CPU among tasks.
A variety of scheduling algorithms have been explored and
implemented.
The general trade-off the simplicity and the optimality.
Challenges for an RTOS Different performance criteria.
GPOS: Maximum average throughput.
RTOS: Deterministic behavior (also small memory usage, low power consumption).
A Theoretically optimal schedule does not exist.
Hard to get complete knowledge – task requirements and hard properties.
The requirements can be dynamic (i.e., Time varying) – adaptive scheduling.
180. Non Real - Time Systems usually use Non-Preemptive Scheduling
Once a task starts executing, it completes its full execution
Most RTOS perform priority-based preemptive task scheduling.
Basic rules for priority based preemptive task scheduling
The Highest Priority Task that is Ready to Run, will be the Task
that Must be Running.
Priority based Preemptive Task Scheduling:
Every Task in a software application is assigned a priority.
Higher Priority = Higher Need for Quick Response.
Follows nested preemption.
181. Static Priority:
A task is given a priority at the time it is created, and it keeps this priority during
the whole lifetime.
The scheduler is very simple, because it looks at all wait queues at each priority
level, and starts the task with the highest priority to run.
Dynamic Priority:
The scheduler becomes more complex because it has to calculate task’s priority
on-line, based on dynamically changing parameters.
Earliest-deadline-first (EDF) --- A task with a closer deadline gets a higher
scheduling priority.
Rate-monotonic scheduling
A task gets a higher priority if it has to run more frequently.
This is a common approach in case that all tasks are periodic. So, a task that has to run every n
milliseconds gets a higher priority than a task that runs every m milliseconds when n<m.
182. Nested Preemption
Timeline for Priority-based Preemptive Scheduling
RT
OS
RT
OS
RT
OS
RT
OS
High-Priority Task
Mid-Priority Task Mid-Priority Task
Low-Priority Task
Trigger_1
Trigger_2
Time
Low-Priority Task
183. Task Switch
Each time the priority-based preemptive scheduler is alerted by an
External world trigger / Software trigger it shall go through the
following steps that constitute a Task Switch:
Determine whether the currently running task should continue to run.
Determine which task should run next.
Save the environment of the task that was stopped (so it can
continue later).
Set up the running environment of the task that will run next.
Allow the selected task to run.
A Non Real time operating system might do task switching only at
timer tick times.
Even with preemptive schedulers a large array of tasks is searched
before a task switch.
A Real time OS shall use Incrementally arranged tables to save on
time
184. Number of Tasks that can be Scheduled
Using Real Time
Operating System
Task
Switching
Time
General-Computing
Non-Real-Time
Operating System
Task Switch Timing :
185. Schedulability:
A schedule is an ordered list of tasks (to be executed) and a
schedule is feasible if it meets all the deadlines
A queue (or set) of tasks is schedulable if there exists a schedule
such that no task may fail to meet its deadline
Running
New Tasks
Scheduling
Dispatching
Termination
Preemption
203. EE6602-EMBEDDED SYSTEMS – TWO MARKS WITH
ANSWERS
UNIT-I
1. List out the changes in building an embedded
system.
a) Amount and type of Hardware needed
b) Clock Rate Reduction
c) Voltage Reduction
d) Process deadlines
e) Flexibility and upgrade ability
f) Wait, stop and cache disable instructions
g) Minimizing the power consumption
2. What is the need of Watch dog timer?
Watch dog timer is a timer device that can be set
for a preset time interval and an event must occur
during that interval else the device will generate
the timeout signal. It resets the processor in case
the program gets stuck for an unexpected length
of time.
3. What are the steps involved in build process?
Building Embedded systems can be focused into
technical perspective such as
a) Software perspective
b) Hardware perspective
4. Mention the classifications of Embedded
Systems.
Embedded systems can be classified into three
types such as
a) Small scale Embedded systems
b) Medium scale Embedded systems
c) Sophisticated Embedded systems
5. Define Embedded system.
A system that has embedded software in a
computer Hardware that makes it a system
dedicated for an application or a specific part of
an application or product or a part of a larger
system.
6. Define Real Time Clock.
Real time clock is a clock that causes occurrences
of regular interval interrupts on its each tick
(timeout). An interrupt service routine executes
on each timeout (overflow) of this clock. The
RTC is used in system to save the current time
and date. The RTC is also used in a system to
initiate return of control of the system after the
preset system clock periods.
7. Define Counting Device.
A counting device is a device that counts the
input for events that may occur at irregular or
regular intervals. The count gives the number of
input events or pulses since it was last read.
8. Define In Circuit Emulator.
In circuit emulators are Hardware tools that both
provide that visibility and behave the same as the
component being emulated. In circuit emulator
which is emulating the microprocessor. It used to
debug the software of an embedded system. It
operates by using a processor with the additional
ability to support debugging operations as well as
to carry out the main function of the system.
9. What are the three modes are usually supported
in DMA operations?
a) Single transfer at a time and then release of
the hold on the system bus.
b) Burst transfer at a time and then release of
the hold on the system bus.
c) Bulk transfer and then release of the hold on
the system bus after the transfer is
completed.
10. Define Cross Compiler.
A cross compiler is a kind of a compiler that runs
on one type of machine but generates code for
another machine. After compilation the
executable code is downloaded to the embedded
system by a serial link or perhaps burned in a
PROM and plugged in.
Extra Questions: 1) Draw the Components of an
Embedded System Hardware.
2) Mention the applications of different
classifications of embedded system.
UNIT-II
1. How SPI is differed from other serial interfaces?
a) It is faster than asynchronous serial.
b) The receive hardware can be a simple shift
register.
c) It supports multiple slaves.
2. What is the need for device driver?
A device driver is a particular form of software
application that is designed to enable interaction
with hardware devices. Without the required
device driver, the corresponding hardware device
fails to work. The main purpose of a device
driver is to instruct a computer on how to
communicate with the input/output device by
translating the operating systems I/O instructions
into a language that a device can understand.
3. Mention the features of CAN and SPI serial
interfaces.
Features of CAN: a) It has a BIU b) It has three
standards – 33 kbps CAN, 110kbps Fault
204. tolerance CAN, 1 Mbps High Speed CAN c) It
has a serial line, which is bidirectional.
Features of SPI: a) 16 bit shift registers b) Slave
in, master out I/O pin c) Slave out, master in I/O
pin c) DMA support d) Upto 66 MHZ operation
4. Write the generic functions of device drivers.
The generic functions used for the commands to
the device are device create (), open(), connect(),
bind(), read(), write(), ioctl().
5. What are handshaking signals?
Handshaking signals are used to exchange before
storing the bits at the port buffer or before
accepting the bits from the port buffer or the
signals to setup or terminate the communication
between two source and destination.
6. Define UART.
UART is a standard Asynchronous serial input
and output port for serial bits. UART usually
sends a byte in 10-bits format or 11 bits format.
The 10 bits format is used when a start bit
preceded the 8 bit message and stop bit succeeds
the message. An 11 bit format is used when a
special bit also precedes the stop bit.
7. Define bus arbitration.
Bus arbitration is a process when multiple
controller or processors attempt to transmit and
access the bus at the same instant, but only one
transmitter is allowed to transmit and access at
that instant.
8. What is half duplex and full duplex?
Half duplex: It is a serial port having one
common I/O line or channel. For example, in a
telephone line, message flows one way at an
instance.
Full duplex: It is a serial port having two distinct
I/O lines or communication channels. For
example, a modem connection to the computer
COM port. There are two lines TxD and RxD at 9
pins or 25 pins connector. Message flows both
ways at an instance.
9. What is meant by bus master?
Bus master is a processor, device or system
which synchronously or asynchronously controls
the input and outputs to the bus at selected
instants.
10. What is COM port?
It is a port at the computer where a mouse,
modem, serial printer or mobile serial printer or
mobile smart phone cradle connects for serial
I/Os in UART mode and there are handshaking
signals for exchange of signals before UART
mode communication.
Extra Questions: 1) Mention the disadvantages of I2
C
Bus.
2) Mention the disadvantages of SPI
interface.
3) Draw the Asynchronous Serial input
RxD at UART COM port.
4) Draw the bit formats of UART
protocol
UNIT-III
1. What is State Machine model?
The State Machine model is used for modeling
reactive or event driven embedded systems
whose processing behavior are dependent on state
transitions.
2. Write about the process involved in co design.
Hardware software co-design is the modem
approach for interactive together design of
hardware and firmware for embedded systems.
The fundamental issues of co-design are selecting
the model, selecting the architecture, selecting the
language and partitioning system requirements
into hardware and software.
3. Mention different models used for the
development of an embedded system.
a) Linear or waterfall model
b) Iterative or Incremental or fountain model
c) Prototyping model
d) Spiral model
4. What is EDLC and write the objectives of
EDLC?
Embedded Product Development Life Cycle
(EDLC) is an Analysis Design Implementation
based standard problem solving approach for
Embedded Product Development.
EDLC has three primary objectives, namely a)
Ensure that high quality products are delivered to
end user b) Risk minimization and defect
prevention in product development through
project management c) Maximize the
productivity.
5. What are the different phases of EDLC?
EDLC has following different phases, Need,
Conceptualization, Analysis, Design,
Development and Testing, Deployment, Support,
Upgrades and Retirement or disposal.
6. What is VLIW?
Very Long Instruction Word (VLIW) architecture
implements multiple functional units in the
datapath. The VLIW instruction packages one
205. standard instruction per functional unit of the
datapath.
7. What is SIMD architecture?
In Single Instruction Multiple Data (SIMD)
architecture a single instruction is executed in
parallel with the help of the processing elements.
The scheduling of the instruction execution and
controlling of each processing elements is
performed through a single controller. It forms
the basis of Re-configurable processor.
8. What is MIMD architecture?
The processing elements of the Multiple
Instruction Multiple Data (MIMD) architecture
execute different instructions at a given point of
time. It forms the basis of multiprocessor
systems. The processing elements in a
multiprocessor system communicate through
mechanisms like shared memory and message
passing.
9. What is controller architecture?
The controller architecture implements the finite
state machine model using a state register and
two combinational circuits. The state register
holds the present state and combinational circuits
implement the logic for next state and output.
10. What is parallel processing architecture?
Parallel processing architecture implements
multiple concurrent processing elements (PEs)
and each processing element may associate a
datapath containing register and local memory.
Example: Single Instruction Multiple Data
(SIMD), Multiple Instruction Multiple Data
(MIMD)
Extra Questions: 1) What is RISC?
2) What is SISC?
3) What is Datapath Architecture?
4) What is DFG model?
5) Define object oriented model.
UNIT IV
1. Define thread and process.
Thread: Thread is a single unit of execution and
is part of process. A thread does not have its own
data memory and heap memory. A thread cannot
live independently, it lives within the process.
Threads are very inexpensive to create.
Process: Process is a program in execution and
contains one or more threads. Process has its own
code memory, data memory and stack memory. A
process contains at least one thread. Processes are
very expensive to create, involved many OS
overhead.
2. What is multiprocessing and multitasking
system?
Multiprocessing systems contain multiple CPUs
and are capable of executing multiple processes
simultaneously.
Multitasking is the ability of an operating system
to hold multiple processes in memory and switch
the processor from executing one process to
another process.
3. What is semaphore? Where it is used?
Semaphore is a sleep and wakeup based mutual
exclusion implementation for shared resource
access. Semaphore is a system resource and the
process which wants to access the shared
resource can first acquire this system object to
indicate the other processes which wants the
shared resources that the shared resource is
currently acquired by it.
4. Compare preemptive and non-preemptive
scheduling.
Preemptive scheduling: It is a multitasking model
in which a currently running task/process is
preempted to execute another task / process.
Non-preemptive scheduling: It is a multitasking
model in which a task gets a chance to execute
when the currently executing task relinquished
the CPU or when it enters a wait state.
5. What are functions of RTOS?
RTOS can perform the following functions:
a) Determines which execution entities in the
application should control the CPU, in what
order and how much time is allowed for each
before giving up processor control.
b) Handles input and output to and from
attached hardware devices.
c) Manages the sharing of internal memory
among multiple tasks.
d) Sends messages about the status of operation
and any errors that may have occurred.
6. What is IPC?
The mechanism through which processes/tasks
communicate each other is known as Inter
Process/Task Communication (IPC). Inter
process communication is essential for process
co-ordination.
7. What is Mutex?
Mutex is the binary semaphore implementation
for exclusive resource access under certain OD
kernel.
8. What is deadlock? What are the different
conditions favouring deadlock?
206. Deadlock is a situation where none of the
processes are able to make any progress in their
execution. Deadlock is the condition in which a
process is waiting for a resource held by another
process which is waiting for a resource held by
the first process. The different conditions
favouring a deadlock situation are a) Mutual
exclusion b) Hold and wait c) No resource
preemption d) Circular wait.
9. What is context switching?
Whenever a CPU switching happens, the current
context of execution should be saved to retrieve it
at a later point of time when CPU executes the
process, which is interrupted currently due to
execution switching. The context saving and
retrieval is essential for resuming a process
exactly from the point where it was interrupted
due to CPU switching. The act of switching CPU
among the processes or changing the current
execution is known as context switching.
10. What are Hard real time systems?
Hard Real Time means strict adherence to each
task schedule. A hard real time system must meet
the deadlines for a task without any slippage.
Missing any deadline may produce catastrophic
results for head real time systems, including
permanent data lose and irrecoverable damages to
the system/users. Example: Air traffic control,
Nuclear power plant control, Anti-lock Brake
systems of vehicles etc.,
11. What are Soft real time systems?
Soft Real Time Systems does not guarantee
meeting deadlines, but offer the best effort to
meet the deadline. Missing deadlines for tasks are
acceptable for a soft real time system if the
frequency of deadline missing is within the
compliance limit of the quality of service.
Example: Telecom, Networks, Web services,
ATM etc.,
Extra Questions: 1) What is task scheduling in the
operating system context?
2) What are the characteristics of
RTOS?
3) What is priority inversion and
priority inheritance?
4) Define throughput.
5) What are the different states of Task
and process?
UNIT V
1. Define MUCOS.
MUCOS is a portable, ROMable, scalable,
preemptive, Real Time and Multitasking Kernel.
It is used in over thousands of applications,
including automotive, avionics, consumer
electronics, medical devices, military aerospace,
networking, system-on-chip development.
2. What is OEM?
OEM is a Original Equipment Manufacturer is a
company that makes a part or subsystem that is
used in another company’s end product. For
example, if ACME Manufacturing Company
makes power chords that are used on IBM
computers, ACME is an OEM.
3. List some applications Embedded systems.
a) Automotive chocolate vending machine b)
Washing or cooking system c) Computer
networking systems d) Banking systems like
Bank ATM, e) Entertainment systems like
video game f) Security products and high
speed Network security.
4. What are the events involved in smart card
systems?
a) On power up by radiation powered charge
pump supply of the card, a signal to start the
system boot program at reset task.
b) Card start request Header message to task-
Read port from reset task.
c) Host authentication request start message to
task-Read port from reset task to enable
requests for Port-IO
d) User PW verification message through Port-
IO from host.
e) Card application close request Appl Close
message to Port_IO
5. What is meant by LIN?
Local Interconnect Network (LIN) bus is a single
master multiple slave communication interface.
LIN is a low speed, single wire communication
interface with support for data rates upto 20 kbps
and is used for sensor/actuator interfacing.
6. What is MOST?
The media oriented system transport (MOST) bus
is targeted for automotive audio / video
equipment interfacing. MOST bus is a
multimedia fibre-optic point to point network
implemented in a star, ring or daisy chained
topology over optical fibres cables.
7. What are the key players of the Automotive
Embedded Market?
207. The key players of the automotive embedded
market can be classified into a) Silicon providers
b) Tools and platform providers c) Solution
providers.
8. What is meant by ECU? And write the
classifications of ECUs.
Automotive Embedded Systems are normally
built around Microcontrollers or DSPs or a hybrid
of the two and are generally known as Electronic
Control Units (ECUs). The various types of
ECUs can be classified into: a) High speed
Electronic Control Units (HECUs) b) Low speed
Electronic Control Units (LECUs)
9. What are the applications of MUCOS?
MUCOS is widely used in many fields such as a)
cameras b) Automotive c) Medical devices d)
Aerospace e) Networking.
10. Name some serial buses used in Automotive
communication.
The most widely used serial buses for automotive
communication are a) Controller Area Network
(CAN) b) Local Interconnect Network (LIN) c)
Media Oriented System Transport (MOST) Bus.
Extra Questions: 1) What is ACVM?
2) Define CAN.
PART B
UNIT-I
1. Draw and explain the components of Embedded
systems.
2. Explain the Build process of a embedded
systems.
3. Draw and explain the structural units of an
embedded systems.
4. Explain DMA with neat sketch.
5. Explain in detail memory management methods.
6. Explain about timer and counting devices.
7. Explain in detail about Incircuit emulator and
target hardware debugging.
UNIT-II
1. Explain in detail different Bus arbitration
methods.
2. Draw and explain Serial peripheral Interface
(SPI)
3. Draw and explain CAN protocol.
4. Explain in detail I2
C Bus.
5. Explain in detail RS 232 standard.
6. Explain the need for device drivers.
7. Explain parallel port interfacing with
UNIT-III
1. Explain the objectives of EDLC.
2. Explain in detail about different phases of EDLC.
3. Explain the different models of EDLC.
4. Explain in detail DFG and CDFG model.
5. Explain the FSM with an example. (Seat belt
warning system, automatic tea, coffee vending
machine, Coin inserted public telephone
machine)
6. Explain sequential and concurrent model.
7. Explain object oriented model.
8. Explain in detail the issues in Hardware and
software Co design.
UNIT IV
1. Explain in detail the basics of operating systems.
2. Explain in detail tasks, process and thread.
3. Explain how the interrupt routines are handled by
RTOS.
4. Explain in detail about the Inter process
communication and context switching.
5. Explain the task synchronous issues in detail.
6. Explain ‘the Dining philosopher’s problem.
7. Explain priority inversion and priority
inheritance.
UNIT V
1. With suitable diagram explain in detail about the
concept of washing machine application.
2. With suitable diagram explain in detail about the
concept of smart card application.
3. With suitable diagram explain in detail about the
concept of automotive application.
4. With suitable diagram explain in detail about the
concept of automatic chocolate vending machine
application.
208. EE6602 – Embedded system Possible Questions
Unit 1
1. List and explain the hardware units that must be present in the embedded systems.
2. Explain the functional building blocks of an Embedded System.
3. Sketch and explain the structural units in processor. Also what are the structural units
available in advanced processors?
4. (i) Summarize In-circuit emulator (7)
(ii) Write a short notes on Watch dog timer (6)
5. (i) Briefly explain the classifications of embedded systems with an example.(6)
(ii) Explain the various form of memories present in an embedded system (7)
6. With a neat diagram explain the working of Direct memory Access
7. Discuss in detail about the timer and counter.
8. With a neat diagram, explain the working of Direct Memory Access (DMA) and
mention the Memory Management methods
Unit 2
1. Explain in detail about SPI communication protocol and its interfacing techniques
2. Explain with all necessary sketches to enable intra communications among
peripherals using I2C bus
3. Demonstrate the signals using a transfer of bytes when using the I2C bus and also the
format of bits at the I2C bus with diagram
4. Explain the physical layer of the I2C and explain its operation with data frame
5. Draw the physical layer of CAN and explain its operation with data frame
6. (i) Compare the RS232C and RS485 serial interface (8)
(ii) Compare the advantages and disadvantages of data transfer using serial and
parallel port devices (8)
7. Explain the working principle of RS 232 serial communication standard in detail.
8. Why we need device driver? How do you write a device driver? List the steps
involved in writing a device driver.
Unit 3
1. Explain the different phases of embedded product development life cycle
2. Explain the following models adopted in embedded product development
a) Iterative/Incremental or Fountain model (7)
b) Prototyping/Evolutionary model (6)
3. Draw the neat sketch of Incremental model and spiral model. Also mention its
advantages and drawbacks.
4. Design a FSM model of an automotive seatbelt warning system
5. Design an automatic tea/coffee vending machine based on FSM model
209. 6. What is meant for hardware software co-design? Explain in detail about the
fundamental issues involved in it.
7. Explain how the embedded system is designed by using sequential program model
and concurrent process model with suitable example
Unit 4
1. What is the structure of a real time operating system? Explain in detail about the
Kernel, Process, and Thread and Task
2. Explain in detail about Task, Process and threads.
3. Explain the different types of preemptive and non-preemptive scheduling algorithms
with suitable examples.
4. Explain the terminologies Semaphores, Mailbox, Pipes and Shared memory in RTOS
5. What is meant by semaphore? Explain the two types of semaphore with suitable
examples
6. Define massage passing. Explain different massage passing technique in embedded
system
7. Explain priority inversion and priority inheritance in detail
8. Explain how the interrupt routines are handled by RTOS and illustrate the features of
VX Works
Unit 5
1. With suitable diagram explain in detail about the concept of washing machine
application
2. Elucidate the selection of processor and memory for any one embedded applications
with suitable diagram in detail
3. With suitable diagram Explain in detail about the concept of Smart card
4. Explain the following in designing Smart Card
(i) Requirements
(ii) Class diagram
(iii) Smart card hardware
(iv) Synchronization Model
Part – C
1. List the tasks involved in the adaptive cruise control in an automobile system. And
explain the inter process communication functions required and their uses in ACC.
2. Explain the various steps involved in design automotive application
3. Explain with a block diagram the ECUs in Present day automobiles
4. Three process with a process IDs P1,P2,P3 with estimated completion time 10,5,7
millisecond respectively enters the ready queue together .A new process P4 with
estimated completion time 2ms enters the ready queue after 2ms.Assume all the
210. process contain only CPU operation and no I/O operation are involved .Calculate and
compare the waiting time and Turn Around Time (TAT) for each process and the
average waiting time and Turn Around Time in SJF algorithm using Non-Preemptive
and Preemptive Scheduling
5. (i) Three process with a process IDs P1,P2,P3 with estimated completion time 6,4,2
millisecond respectively enters the ready queue together in the order P1,P2,P3.
Calculate the waiting time and Turn Around Time (TAT) for each process and the
average waiting time and Turn Around Time (Assume there is no I/O waiting for the
process ) in RR algorithm with time slice = 2ms.
(ii) The processes with process IDs P1, P2, P3 with estimated completion times 10,2 ,6
milliseconds respectively enters the ready queue together. Calculate the waiting time
and turnaround time (TAT) for each process and average waiting time and average TAT
in FIFO algorithm.
6. Explain the finite state machine model for Public operated telephone System
Part A
Unit 1
1. What are the types of embedded systems?
2. Illustrate the steps involved in build process
3. What is real time system?
4. Differentiate hard and soft real time systems.
5. Define embedded system.
6. List out the challenges in building an embedded system
7. What is need of DMA?
8. What is real time clock?
9. What is the need of watch dog timer?
10. What is timing device?
Unit 2
1. What is MOSI & MISO?
2. Mention the features of CAN and SPI interfaces
3. List the features of CAN
4. Define UART
5. What is half and full duplex?
6. What is a handshaking signal?
7. What is the use of NACK Signal?
8. Draw the data framework of I2C
9. List out the standards for I2C bus with its different speed levels.
211. 10. What are the advantages of RS 485 than RS 422?
Unit 3
1. What are the different phases of EDLC?
2. What is meant by cost benefit analysis?
3. Define deployment phase.
4. What are the objectives of EDLC?
5. What are the process involved in Co-design?
6. What is the difference between prototyping model and fountain model?
7. What is meant by modeling in EDLC?
8. What is the difference between Linear and fountain model?
9. Model the Control data flow graph with an example.
10. What is the difference between Linear and spiral model?
Unit 4
1. Define semaphore signaling
2. What do you understand by real time scheduling
3. Compare preemptive and non-preemptive scheduling
4. Define thread and process
5. What are the functions of RTOS
6. Name any two mailbox related functions.
7. Name any two important RTOS.
8. What is Round robin algorithm?
9. Define Turn Around Time (TAT).
10. What is deadlock? What are the different conditions favouring deadlock?
Unit 5
1. List some applications of embedded systems.
2. What are the events involved in the smart card application.
3. List the design metrics of Smart Card
4. Draw the system components in the Smart Card.
5. What are the sensors and actuators of Washing machine?
6. What is ACHVWLT in Automobiles
7. List the design metrics of ACC
8. What is meant by ACC?
9. Define ECU in CAR.
