With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.

1. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 835 – 840
_______________________________________________________________________________________________
835
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic
Unit
Er. Ravijot Kaur
Department of Electronics and Communication,
Punjabi University
Patiala, India
ravijot0630@gmail.com
Er. Amandeep Singh Bhandari
Department of Electronics and Communication,
Punjabi University
Patiala, India
singh.amandeep183@gmail.com
Abstract: With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing
exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising
technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In
this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates.
The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an
arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations:
Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
Keywords: Reversible logic, ALU, Fault tolerant, Parity Preserving gates, Quantum cost, Garbage Outputs.
__________________________________________________*****_________________________________________________
I. INTRODUCTION
A. Principles of Reversible Logic
The classical computational process which is irreversible, one
bit of information is lost for each logical operation carried out
by it. But in 1961, Rolf Landauer’s principle states that for
each bit of information lost K.T.ln2 Joules of energy is
dissipated in the form of heat (where K is the Boltzmann’s
constant i.e. 1.38 × 10−23 J/K and T is the absolute
temperature)[1]. However, this loss of energy is neglible for
simple circuits and become significant for complex circuits. At
room temperature T, the amount of heat dissipation is small
(i.e. 2.9×10 -21 joule), but not negligible. In 1973, Bennet
showed that there would be no energy dissipation if
computations are done in the reversible way[2]. Resultantly, a
new paradigm in circuit design evolved with the aim of
reducing the entropy increase and energy dissipation[3].
Further, such a logical structure must possess the same number
of inputs and outputs and a one-to-one mapping between the
input and output states. Any device designed according to the
above constraints is known as a reversible logic device[3].
Reversibility becomes an essential parameter for the future
computer designs[4]. Reversible gates or circuits allow the
reconstruction of the inputs from the observed outputs.
Reversible logic is applicable to the research areas such as low
power CMOS design, optical computing, quantum computing,
bioinformatics, thermodynamic technology, DNA computing
and nanotechnology[4]. A reversible circuit should be
designed using minimum number of reversible logic gates.
B. Parameters of Reversible Logic
There are many parameters for determining the complexity
and performance of circuits in reversible logic circuit design.
The following parameters should be reduced for the efficient
reversible circuit design[5].
Gate count (N): This refers to the number of reversible gates
used in circuit.
Constant inputs (CI): The number of inputs that are to be
maintained constant at either 0 or 1 in order to synthesize the
given logical function[5].
Garbage outputs (GO): The number of unused outputs
present in a reversible logic circuit. Garbage outputs can’t be
avoided as these are essential to achieve reversibility.
Quantum cost (QC): This refers to the cost of the circuit in
terms of the cost of a primitive gate.
Gate levels (GL): The number of levels in the circuit which
are required to realize the given logic functions[5].
II. REVERSIBLE LOGIC GATES
A. Basic Reversible gates
In classical irreversible gates, input states cannot be
reconstructed from its outputs states[5]. Therefore, reversible
gates are used in which input states can be reconstructed from
the output states. The various reversible gates used in the
proposed design are 3*3 Peres gate depicted in Fig. 1(a), 4*4
MHNG gate depicted in Fig. 1(b), 4*4 HNG2 gate depicted in
Fig. 1(c).

2. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 835 – 840
_______________________________________________________________________________________________
836
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Fig 1(a): Peres gate
Fig 1(b): MHNG gate
Fig 1(c): HNG2 gate
Fig 1(c): HNG2 gate
B. Fault Tolerant and Parity Preserving Reversible Gates
Fault tolerance is the property that allows a system to operate
appropriately in the situation of failure of some of its
components[5]. In fault tolerant systems, the detection and
also correction of faults become easier and simple. Parity is
used for fault tolerance in many systems. The basic fault
tolerant gate is 3*3 NFT (New Fault Tolerant) gate depicted in
Fig. 2(a). The various parity preserving gates used in the
design are 3*3 F2G (Double Feynman Gate) gate depicted in
Fig. 2(b) and IG (Islam Gate) gate depicted in Fig. 2(c).
Fig 2(a): NFT gate
Fig 2(b): F2G gate
Fig 2(c): IG gate
Fig 2: Fault tolerant and Parity Preserving gates
III. ARITHMETIC LOGIC UNIT PROPOSED DESIGN
ALU is a multi-operation, combinational logic digital function
generator[6]. ALU is an integral part of any computing system
and provides many arithmetic and logical operations such as
addition, subtraction, multiplication, AND, XOR, TRANSFER
of inputs etc. The proposed design of ALU performs 7
different arithmetic and logical operations. Depending upon
the select lines, the ALU design selects the operation to be
performed[7]. The selection procedure of the proposed ALU
design is shown in Fig 3.
Fig 3: ALU design
Table 1: OPERATIONS PERFORMED BASED ON THE
CONTROL SIGNAL

3. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 835 – 840
_______________________________________________________________________________________________
837
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
The ALU design inhibits the function generator property to
process the input signals A and B under the control of control
signals s0, s1 and s2[8]. The operations performed based on
the control signals are shown in Table 1. Total seven
arithmetic and logical operations are performed by the ALU.
A. 32-BIT FULL ADDER
The proposed ALU design consists of a 32-bit reversible full
adder shown in Fig 4. The adder design consists of 32 MHNG
(Modified HNG) gate. In each MHNG gate, first two bits
carries the input bits, the third bit carries the initial carry and
the last bit is maintained as zero i.e. constant input. The third
and fourth output of the MHNG gate indicates the sum and
output carry respectively and the second output is unused i.e.
garbage output. The first output acts as the logical operation to
transfer the first input vector A which reduces the garbage
outputs of the proposed ALU design. The proposed adder is
efficient in terms of quantum cost as compared to the existing
design[7].
Fig 4. 32-bit Reversible Full Adder Design
B. 32-BIT FULL SUBTRACTOR
The proposed ALU design consists of a 32-bit reversible full
subtractor shown in Fig 5. The subtractor design consists of 32
HNG2 gate. In each HNG2 gate, first two bits carries the input
bits, the third bit carries the initial borrow and the last bit is
maintained as zero i.e. constant input[7]. The third and fourth
output of the HNG2 gate indicates the difference and output
borrow respectively and the first output is unused i.e. garbage
output. The second output acts as the logical operation to
transfer the first input vector B which reduces the garbage
outputs of the proposed ALU design.
Fig 5. 32-bit Reversible Full Subtractor Design
C. 32-BIT MULTIPLIER
The 2-bit multiplier design is shown in Fig. 6 which comprises
of 4 F2G gate, 4 Peres gate and 2 IG gate. By using this 2 bit
multiplier, 4 bit multiplier is designed and further the 4 bit
multiplier is used to design 8 bit multiplier and so on[7]. Thus
a 32-bit multiplier is constructed using four 16 bit multipliers.
The proposed multiplier design is better than the existing
design in terms of quantum cost.
Fig 6. 2-bit Reversible Multiplier
D. LOGICAL UNIT
The proposed ALU performs four logical operations namely
AND, XOR, TRANSFER A, TRANSFER B. The 32-bit AND
and XOR operations are performed using Peres gate and
Transfer of input vectors are obtained by utilizing the garbage
outputs of 32 bit full adder and full subtractor design. This will
reduce the overall garbage outputs of the ALU design, thus,
optimizing the design. The 32-bit AND and XOR operation
design is shown in Fig.7.
Fig 7. 32-bit AND and XOR design
IV. SIMULATION AND SYNTHESIS RESULTS
The proposed 32-bit ALU design is simulated using
MODELSIM ALTERA 6.4a version and synthesized using
XILINX ISE SUITE 13.2 version. VERILOG HDL is used for
simulation and synthesis purpose. The various results of the
ALU design are shown in the figures below.
Fig 8(a). Simulation result of 32-bit Full Adder
G2

4. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 835 – 840
_______________________________________________________________________________________________
838
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Fig 8(b). Simulation result of 32-bit Full Subtractor
Fig 8(c). Simulation result of 32-bit Multiplier
Fig 8(d). Simulation result of 32-bit AND operation
Fig 8(e). Simulation result of 32-bit XOR operation
Fig 8(f). Simulation result of Transfer of A input vector
Fig 8(g). Simulation result of Transfer of B input vector
Fig 8(h). RTL1 schematic of ALU design
Fig 8(i). RTL2 schematic of ALU design
Fig 8(j). Graph showing power consumption of proposed ALU
design
Fig 8(j). Graph showing power consumption of proposed
design w.r.t. junction temperature

5. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 835 – 840
_______________________________________________________________________________________________
839
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Fig 8(i). Graph showing comparison of power consumption of
existing design[7] and proposed design
V. COMPARISON
The proposed ALU design is compared with the existing
design in terms of quantum cost, power consumption and
number of garbage outputs. The comparison results are shown
in table 2 below.
Table 2: Comparison results for proposed design and existing
design[7]
VI. CONCLUSION
The results of the existing ALU and the proposed ALU design
are verified using Modelsim Simulator and synthesized using
Xilinx ISE Design Suite 13.2. The power consumption is
calculated using Xilinx Power Estimator(XPE)-2017.2. The
proposed design is better in terms of Quantum cost and Power
consumption when compared to other conventional ALU
designs and can be used in Low power Applications. The size
of the design is also improved. The proposed design is 32 bit
in size as compared to the design given in [7] which is 16 bit
in size.
REFERENCES
[1] Landauer, R.: Irreversibility and heat generation in the
computing process. IBM J. Res. Dev. 5(3), 183– 191
(1961).
[2] Bennett, C.H.: Logical reversibility of computation. IBM J.
Res. Dev. 17(6), 525–532 (1973).
[3] Matthew Morrison, Nagarajan Ranganathan, “Design of a
Reversible ALU based on Novel Programmable Reversible
Logic Gate Structures”, in IEEE Computer Society Annual
Symposium on VLSI, IEEE, 2011.
[4] Md. Belayet Ali, Hosna Ara Rahman and Md. Mizanur
Rahman, “Design of a High Performance Reversible
Multiplier”, in International Journal of Computer Science
Issues, 2011.
[5] Taranjot Kaur, Nirmal Singh, “Design of Fault Tolerant
Arithmetic and Logical Unit using Reversible Logic”, in
International Conference on Machine Intelligence Research
and Advancement, IEEE, 2013.
[6] Rakshith T.R, Rakshith Saligram, “Parity Preserving Logic
based Fault Tolerant Reversible ALU”, in Proceedings of
2013 IEEE Conference on Information and Communication
Technologies, IEEE, 2013.
[7] Sk. Bajidbi, M.S.S. Rukmini and Y. Ratna Babu,
“Implementation of Reversible Arithmetic and Logical Unit
and Its BILBO Testing”, in Microelectronics,
Electromagnetics and Telecommunications, Lecture Notes in
Electrical Engineering 372, Springer India, 2016.
[8] Zhijin Guan, Wenjuan Li, Weiping Ding, Yueqin Hang Lihui
Ni, “An Arithmetic Logic Unit Design Based on Reversible
Logic Gates”, in International Conference on Communication,
Computers and Signal Processing, IEEE, 2011.
[9] R. Dhanabal, Sarat Kumar Sahoo, V. Bharathi, V. Bhavya,
Patil Ashwini Chandrakant and K. Sarannya, “Design of
Reversible Logic Based ALU”, in Proceedings of the
International Conference on Soft Computing Systems,
Advances in Intelligent Systems and Computing 397,
Springer India, 2016.
[10] Deeptha A, Drishika Muthanna, Dhrithi M, Pratiksha M, B S
Kariyappa, “Design and Optimization of 8 bit ALU using
Reversible Logic”, in IEEE International Conference On
Recent Trends In Electronics Information Communication
Technology, IEEE, 2016.
[11] Jenil Jain, Rahul Aggarwal, “Design And Development of
Efficient Reversible Floating Point Arithmetic unit”, in Fifth
International Conference on Communication Systems and
Network Technologies, IEEE, 2015.
[12] Kunal Jadhav, Aditya Vibhute, Shyam Iyer, R. Dhanabal,
“Novel Vedic Mathematics Based ALU Using Application
Specific Reversibility”, in 9th International Conference on
Intelligent Systems and Control (ISCO), IEEE, 2015.
[13] Ankur Sarker, Hafiz Md. Hasan Babu, Sarker Md Mahbubur
Rashid, “Design of DNA base arithmetic and logic unit”, in
IET journal Nanobiotechnology, Vol. 9, 2015.
[14] Majid Haghparast, Ali Bolhassani, “Optimization Approaches
for Designing Quantum Reversible Arithmetic Logic Unit”, in
Int J. Theory Physics, Springer, 2015.
[15] Subhankar Pal, Chetan Vudadha, Sai Phaneendra P, Sreehari
Veeramachaneni, Srinivas Mandalika, “A New Design of an
n-bit Reversible Arithmetic Logic Unit”, in Fifth International
Symposium on Electronic System Design, IEEE, 2014.
[16] Rakshith T.R, Rakshith Saligram, “Towards the Design of
Fault Tolerant Reversible Circuits Components of ALU using
New PCMF Gate”, in International Conference on Advances
in Computing, Communication and Informatics, IEEE, 2013.
[17] Mozammel H A Khan, “Classical Arithmetic Logic Unit
Embedded on Reversible/ Quantum Circuit”, in International
Conference on Computer and Information Technology, IEEE,
2012.
[18] Bibhash Sen, Manojit Dutta, Debajyoty Banik, Dipak K
Singh, Biplab K Sikdar, “Design of Fault Tolerant Reversible

6. International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169
Volume: 5 Issue: 7 835 – 840
_______________________________________________________________________________________________
840
IJRITCC | July 2017, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
Arithmetic Logic Unit in QCA”, in International Symposium
on Electronic System Design, IEEE, 2012.
[19] Matthew Arthur Morrison, “Design of a reversible ALU
based on Novel Reversible Logic Structures”, USF Graduate
School, 2012.
[20] B.Ravali, M.Micheal Priyanka, T.Ravi, “Optimized
Reversible Logic Design for Vedic Multiplier”, in
International Conference on Control, Instrumentation,
Communication and Computational Technologies, IEEE,
2015.
[21] Pragya Gupta, Priyanka Shah, “A Study of Reversible Logic
Gates and their Applications”, in International Journal of
Advanced Engineering and Global Technology , 2015.
[22] Ashima Malhotra, Charanjit Singh, Amandeep Singh,
“Efficient Design of Reversible Multiplexers with Low
Quantum Cost and Power Consumption”, International
Journal of Emerging Technology and Advanced Engineering
(IJETAE), Volume 4, Issue 7, July 2014, pp 518 – 523.
[23] Ashima Malhotra, Charanjit Singh, Amandeep Singh,
“Efficient Design of Reversible Multiplexers with Low
Quantum Cost’’, International Journal of Engineering
Research and Applications, Volume 4, Issue 7, July
2014.pp.20-23.
[24] Ankush, Amandeep Singh Bhandari, “Review Paper on
Reversible Logic Gate”, International Journal for Research in
Electronics & Communication Engineering, vol. 1, Issue 7,
(2016).
[25] Sukhjeet Kaur, Amandeep Singh, “Design and Performance
Analysis of Encoders using Reversible logic gates”
International Journal of Scientific & Engineering Research,
Volume 6, Issue 6, June-2015.pp.327-332.
[26] Manjinder Pal Singh, Birinderjit Singh, Amandeep Singh,
“Performance Analysis of Low Power Decoders Using
Reversible Computing”, International Journal of Research,
Volume 2, Issue 11, November 2015.
[27] Ankush, Amandeep Singh Bhandari, “Design & Performance
Analysis of Low Power Reversible Carry Skip Adder”, IOSR
Journal of VLSI and Signal Processing, vol. 6, Issue 4, Ver.
II,(2016),pp.33-39.
[28] Ankush, Amandeep Singh Bhandari, “Design & Performance
Analysis of Low Power Reversible Residue Adder”,
International Journal of Hybrid Information Technology, vol.
9,Issue 9,(2016),pp.93-102.
[29] Amandeep Singh Bhandari and Priya Sharma, “Introduction
to Reversible Logic and Mathematical Derivation for V and
V+ Gates”, International Journal of Computer Applications
(0975 – 8887) Volume 153 – No5, November 2016, pp 14-18.
[30] Prinkle Wadhawan, Ravijot Kaur, Amandeep Singh, “A
REVIEW ON QUANTUM DOT CELLULAR
AUTOMATA”, International Journal of Electrical and
Electronics Engineers, Volume 9, Issue 1, 2017, pp319-327.