Slides for the paper "An algebra for VHDL with signal attributes" given at Asia-Pacific Conference on Hardware Definition Languages, Bangalore, India, December 1995. A preprint of the full paper is at http://www.academia.edu/2493996/An_algebra_for_VHDL_with_signal_attributes .

1. ?
A Process Algebra for VHDL
with Signal Attributes
Peter T. Breuer, Natividad Mart´ınez Madrid, Luis S´anchez, Carlos Delgado Kloos
Universidad Polit´ecnica de Madrid {ptb,nmadrid,lsanchez,cdk}@dit.upm.es
APCHDL, Bangalore, India – January 1996 1

2. Contents ?
• Introduction
• Addition to VHDL syntax
• Signal attributes
• Algebra
• Laws and example
APCHDL, Bangalore, India – January 1996 2

3. Aims ?
Native process algebra for VHDL
[Breuer & Mart´ınez Madrid, Euro-VHDL’95]
+ VHDL signal attributes
[Breuer et al., APCHDL’95]
l
APCHDL, Bangalore, India – January 1996 3

4. VHDL ?
• IEEE, DoD standard VHSIC Hardware Description Language
• standards 1987, 1992
• 70% commercial penetration
• forthcoming VHDL–A extension
• imperative language with temporal constructs
• coded behaviour legally defines compiled hardware function
APCHDL, Bangalore, India – January 1996 4

5. Example A – VHDL code ?
Oscillator process ‘a’
c
c
C<=¬ C after 1ns
wait on C
PROCESS [C:out]
BEGIN
C <= TRANSPORT (NOT C) AFTER 1ns ;
WAIT ON C ;
END
APCHDL, Bangalore, India – January 1996 5

6. Extended VHDL Syntax ?
VHDL ::= Statement [ ; VHDL ]
Statement ::= Channel ⇐ transport Expression after Delay
| wait on Channel
| if Expression then VHDL else VHDL
| while Expression do VHDL
| null
| Promise
Expression ::= Channel [ ’Event | ’Stable | . . . ]
| Constant
Process ::= process [ Channels ] begin VHDL end
| Process || Process
APCHDL, Bangalore, India – January 1996 6

7. Three Images of a Promise ?
[C !
0
0 !
1
1 !
2
0 !
3
1 !
4
0 !
5
1 !
6
0 !
7
1 !
9
0 !
10
1 !
12
0 !
13
1 !
15
0 !
16
1 !
17
0 !
18
1 !
19
0 !
20
1 !
21
0]
—oOo—
-
1 2 3 4 5 6 7 9 10 12
13
15
16
17
18
19
20
21
Time
—oOo—
C <= transport 1 after 1ns;
C <= transport 0 after 2ns;
...
C <= transport 0 after 21ns;
APCHDL, Bangalore, India – January 1996 7

8. Example A – extended VHDL code ?
Oscillator process ‘a’
[ C!
0
0 ] ; -- promise replaces process header
WHILE true DO -- loop replaces process body
C <= TRANSPORT (NOT C) AFTER 1ns ;
WAIT ON C ;
END
APCHDL, Bangalore, India – January 1996 8

9. Example B – VHDL code ?
Follower process ‘b’
c
c
D<= ? after 1ns
wait on C,E
PROCESS [C,E:in, D:out]
BEGIN
IF (E’event & E=0) THEN
D <= TRANSPORT 0 AFTER 1ns ;
ELSE D <= TRANSPORT C AFTER 1ns ;
END IF ;
WAIT ON C,E ;
END
APCHDL, Bangalore, India – January 1996 9

10. Example B – extended VHDL code ?
Follower process ’b’
[ D!
0
0 ]C=0,E=0 ; -- promise with input channels
WHILE true DO
IF (E’event & E=0) THEN
D <= TRANSPORT 0 AFTER 1ns ;
ELSE D <= TRANSPORT C AFTER 1ns ;
END IF ;
WAIT ON C,E ;
END
APCHDL, Bangalore, India – January 1996 10

11. Representing Attributes ?
The ’Event attribute is indicated by an asterisk:
[C !
0
0 !
1
1∗ !
2
0∗ !
3
1∗ !
4
0∗ !
5
1∗ !
6
0∗ !
7
1∗ !
9
0∗ . . .]
’Last Event is represented by a superscript:
[C !
0
0 !
1
11 !
2
01 !
3
11 !
4
01 !
5
11 !
6
01 !
7
11 !
9
02 . . .]
The ’Last Value attribute subscripts the promise values:
[C !
0
0 !
1
10 !
2
01 !
3
10 !
4
01 !
5
10 !
6
01 !
7
10 !
9
01 . . .]
Etc.
Signal attributes are real attributes of signal values.
APCHDL, Bangalore, India – January 1996 11

12. Algebra Syntax ?
Algebra ::= VHDL embedded code
| Event Algebra event prefixed to code
| Algebra Algebra synchronous parallelism
| chaos the chaotic process
| Algebra | Algebra nondeterministic choice
| stop no choice at all
Event ::= Channel ! Value value output on channel
APCHDL, Bangalore, India – January 1996 12

13. Algebraic Laws ?
If tk < t ≤ tk+1:
[C !
0
c0 . . . !
tn
cn]; C ⇐ transport c after tns = [C !
0
c0 . . . !
tk
ck !
t
c]
If tn < t:
[C !
0
c0 . . . !
tn
cn]; C ⇐ transport c after tns = [C !
0
c0 . . . !
tn
cn !
t
c]
Let tk be the first time at which ck = c0:
[C !
0
c0 . . . !
tk
c∗
k . . . !
tn
cn]; wait on C = C!c0 . . . C!c0
tk times
[C !
0
c∗
k . . . !
tn
cn]
APCHDL, Bangalore, India – January 1996 13

14. Example A – algebraic reduction ?
Oscillator process ‘a’
[C !
0
0]; a
= [C !
0
0]; C ⇐ transport not C after 1ns; wait on C; a
= [C !
0
0 !
1
1∗]; wait on C; a
= C!0 [C !
0
1∗]; a
. . .
= C!0 C!1∗ [C !
0
0∗]; a
APCHDL, Bangalore, India – January 1996 14

15. Example A – visualization ?
z z
z
z
z
z
z
z&%
'$-
?
J
J
J
J
J
J
J
?
J
J
J
J
J
J
J
?
?
J
J
J
J
J
J
J
C!0 C!0
C!1
C!1 C!0
[C!
0
0];a
=
[C!
0
1];a
=
[C!
0
0];a
=
APCHDL, Bangalore, India – January 1996 15

16. Example B – final visualization of follower ?
............................................................................
~~
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
~
~
~
~
~ ~.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... 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C!c E!0
(E = 1∗)
C!c E!1
C!c E!0*
C!c E!0(E = 0∗)
(E = 1∗)
(E = 0∗)
(E = 1) (E = 0)
C!c E!1*
C!c E!1
C!c D!0 E!1*
C!¬ c D!0 E!0*
C!¬ c E!1
C!¬ c E!1*
C!¬ c E!1
C!¬ c D!0 E!0*
C!¬ c D!0 E!0*
C!¬ c E!0
C!¬ c E!0
C!¬ c E!1*
APCHDL, Bangalore, India – January 1996 16

17. Example B – reduced state diagram ?
Follower ‘b’ with reset line E inactive
z z
zz
%
'$
%
'$
‚
s
'
E
T
c
H
HH
HH
HH
HH
HHH
HH
HHH
H
HH
HH
HH
HH
HHH
HH
HHHrrj
rr‰
D!1 C!0
D!0 C!0
D!0 C!1
D!1 C!1
D!1 C!1
D!0 C!0
P Q
RS
D!0 C!1
D!1 C!0
z
z
%
'$
%
'$
%
'$
'
T
c
©
PQ
RS
D!0 C!0
D!0 C!0
D!1 C!1
D!0 C!1 D!1 C!0
APCHDL, Bangalore, India – January 1996 17

18. Summary ?
• Signal attributes fit in with the already developed process algebra
for VHDL
• The right way to treat them is as real attributes of the signal
values
• This technique mechanically reduces unit-delay VHDL code con-
taining attribute references to labelled state transition diagrams.
APCHDL, Bangalore, India – January 1996 18