Digital electronics sequential ckts counters

Digital Electronics
Sequential Circuits: Counters
Nilesh Bhaskarrao Bahadure
nbahadure@gmail.com
https://www.sites.google.com/site/nileshbbahadure/home
July 1, 2021
Nilesh Bhaskarrao Bahadure (PhD) Digital Electronics July 1, 2021 1 / 29

Overview
1 Counters
Classification of counters
Comparison between Synchronous and Asynchronous counters
2 Asynchronous Counter
2-Bit Asynchronous Binary Counter
Asynchronous Decade Counter
3 Synchronous Counter
Ring Counters
Johnson/Twisted-Ring Counters
4 Thank You

Counters

Counters
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal.

In electronics, counters can be implemented quite easily using register-type
circuits such as the flip-flop, and a wide variety of classifications exist:
1 Asynchronous (ripple) counter - changing state bits are used as clocks
to subsequent state flip-flops.

2 Synchronous counter - all state bits change under control of a single
clock.

clock.
3 Decade counter - counts through ten states per stage.

clock.
4 Up/down counter - counts both up and down, under command of a
control input.

clock.
control input.
5 Ring counter - formed by a shift register with feedback connection in
a ring.

clock.
control input.
5 Ring counter - formed by a shift register with feedback connection in
a ring.
6 Johnson counter - a twisted ring counter.

Comparison between Synchronous and Asynchronous
counters
1 In, Asynchronous the clock pulse inputs of all flip flops, except the
first, are triggered not by the incoming pulses, but rather by the
transition that occurs in previous flip flop’s output. Whereas In a
synchronous counter, the input pulses are applied to all clock pulse
inputs of all flip flops simultaneously (directly).

counters
2 Asynchronous counter is also known as serial sequential circuit
whereas Synchronous counter is also known as parallel sequential
circuit.

counters
circuit.
3 Asynchronous counters are slower than synchronous counter whereas
Synchronous counters are faster than asynchronous counter

counters
circuit.
4 Asynchronous circuits are quite difficult to design for a reliable
operation. Whereas Synchronous circuits are easy to design for a
reliable operation.

counters
circuit.
4 Asynchronous circuits are quite difficult to design for a reliable
operation. Whereas Synchronous circuits are easy to design for a
reliable operation.
5 Example of asynchronous counter, Binary Ripple Counter, Up Down
Counter whereas example Synchronous counters Ring Counter,
Twisted ring counter.

Asynchronous Counter
Ripple Counter

Ripple Counter
Asynchronous counters called ripple counters, the first flip-flop is clocked
by the external clock pulse and then each successive flip-flop is clocked by
the output of the receding flip-flop. The term asynchronous refers to
events that do not have a fixed time relationship with each other. An
asynchronous counter is one in which the flip-flops within the counter do
not change states at exactly the same time because they do not have a
common clock pulse.

Figure : 2-Bit Asynchronous Binary Counter

A 2-Bit Asynchronous Binary Counter figure 1 shows a 2-bit counter
connected for asynchronous operation. Notice that the clock (CLK) is
applied to the clock input (C) of only the first flop-flop, FF0, which is
always the least significant bit (LSB). The second flip-flop, FF1, is
triggered by the Q0 out-put of FF0. FF0 changes state at the
positive-going edge of each clock pulse. But FF1 changes only when
triggered by a positive-going transition of the Q0 output of FF0. Because
of the inherent propagation delay tie through a flip-flop, a transition of the
input clock pulse (CLK) and a transition of the Q0 output of FF0 can
never occur at exactly the same time . Therefore, the two flip-flops are
never simultaneously triggered, so the counter operation is asynchronous.

Timing Diagram

Timing Diagram
Applying 4 clock pulses to FF0, Both flip-flops are connected for toggle operation (J=1,
K=1) and initially RESET (Q LOW).

Timing Diagram
K=1) and initially RESET (Q LOW). The positive-going edge of CLK1 (clock pulse1)
causes the Q 0 output of FF0 to go HIGH.

Timing Diagram
causes the Q 0 output of FF0 to go HIGH. At the same time the Q0 output goes LOW,
but it has no effect on FF1 because a positive-going transition must occur to trigger the
flip-flop.

Timing Diagram
flip-flop. After the leading edge of CLK1, Q0=1 & Q1=0.

Timing Diagram
flip-flop. After the leading edge of CLK1, Q0=1 & Q1=0. The positive-going edge of
CLK2 causes Q0 to go LOW. Q0 goes HIGH and triggers FF1, causing Q1 to go HIGH.

Timing Diagram
After the leading edge of CLK2, Q0=0 & Q1=1.

Timing Diagram
The positive-going edge of CLK3 causes Q0 to go HIGH again.

Timing Diagram
The positive-going edge of CLK3 causes Q0 to go HIGH again. Output Q0 goes LOW
and has no effect on FF1. Thus, after the leading edge of CLK3, Q0 & Q1=1.

Timing Diagram
and has no effect on FF1. Thus, after the leading edge of CLK3, Q0 & Q1=1. The
positive-going edge of CLK4 causes Q0 to go LOW, while Q0 goes HIGH and triggers
FF1, causing Q1 to go LOW.

Timing Diagram
FF1, causing Q1 to go LOW. After the leading edge of CLK4, Q0=0 & Q1=0.

Timing Diagram
FF1, causing Q1 to go LOW. After the leading edge of CLK4, Q0=0 & Q1=0. The 2-bit
counter exhibits four different states, as you would expect with two flip-flops (22
= 4).

Timing Diagram
FF1, causing Q1 to go LOW. After the leading edge of CLK4, Q0=0 & Q1=0. The 2-bit
counter exhibits four different states, as you would expect with two flip-flops (22
= 4).
The fourth pulse it recycles to its original state (Q0=0, Q1=0). The term recycles; it
refers to the transition of the counter from its final state back to its original state.

Figure : Timing diagram of 2 bit asynchronous counter

Figure : 3-Bit Asynchronous Binary Counter

It works exactly the same way as a two-bit asynchronous binary counter
mentioned above, except it has eight states due to the third flip-flop.

Figure : Timing diagram of 3 bit asynchronous counter

Asynchronous Decade Counter/BCD Counter/Divide by 10
Counter

Counter
If we take the modulo-16 asynchronous counter and modified it with
additional logic gates it can be made to give a decade (divide-by-10)
counter output for use in standard decimal counting and arithmetic
circuits.

Counter
If we take the modulo-16 asynchronous counter and modified it with
additional logic gates it can be made to give a decade (divide-by-10)
counter output for use in standard decimal counting and arithmetic
circuits.
Such counters are generally referred to as Decade Counters. A decade
counter requires resetting to zero when the output count reaches the
decimal value of 10, ie. when DCBA = 1010 and to do this we need to
feed this condition back to the reset input. A counter with a count
sequence from binary ”0000” (BCD = ”0”) through to “1001” (BCD =
”9”) is generally referred to as a BCD binary-coded-decimal counter
because its ten state sequence is that of a BCD code but binary decade
counters are more common.

Figure : Asynchronous decade counter

Asynchronous Decade Counter...

This type of asynchronous counter counts upwards on each trailing edge of
the input clock signal starting from 0000 until it reaches an output 1001
(decimal 9). Both outputs QA and QD are now equal to logic ”1”. On the
application of the next clock pulse, the output from the 74LS10 NAND
gate changes state from logic ”1” to a logic ”0” level.

This type of asynchronous counter counts upwards on each trailing edge of
the input clock signal starting from 0000 until it reaches an output 1001
(decimal 9). Both outputs QA and QD are now equal to logic ”1”. On the
application of the next clock pulse, the output from the 74LS10 NAND
gate changes state from logic ”1” to a logic ”0” level.
As the output of the NAND gate is connected to the CLEAR ( CLR )
inputs of all the 74LS73 J-K Flip-flops, this signal causes all of the Q
outputs to be reset back to binary 0000 on the count of 10. As outputs
QA and QD are now both equal to logic ”0” as the flip-flops have just
been reset, the output of the NAND gate returns back to a logic level ”1”
and the counter restarts again from 0000. We now have a decade or
Modulo-10 up-counter.

Clock Output bit Pattern Decimal
Count QD QC QB QA Value
1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 Counter Resets its Outputs back to Zero
Table : Decade counter truth table

How to decide number of flip flops in Modulo
Mod -40
Lets say we wish to count from 0 to 39, or mod-40 and repeat. Then the
highest number of flip-flops required would be six, n = 6 giving a
maximum MOD of 64 as five flip-flops would not be enough as this only
gives us a MOD-32.

Synchronous Counter
In synchronous counters, the clock input is connected to all of the
flip-flops so that they are clocked simultaneously. The term synchronous
refers to events that have a fixed time relationship with each other.

Ring Counters

Ring Counters
Ring counters are implemented using shift registers. It is essentially a
circulating shift register connected so that the last flip-flop shifts its value
into the first flip-flop. There is usually only a single 1 circulating in the
register, as long as clock pulses are applied.

Ring Counters...
Figure : Ring counter (Mod -4 Counter)

Ring Counters...

Ring Counters...
In the diagram above, assuming a starting state of Q3 = 1 and Q2 = Q1
= Q0 = 0. At the first pulse, the 1 shifts from Q3 to Q2 and the counter
is in the 0100 state. The next pulse produces the 0010 state and the third,
0001. At the fourth pulse, the 1 at Q0 is transferred back to Q3, resulting
in the 1000 state, which is the initial state. Subsequent pulses will cause
the sequence to repeat, hence the name ring counter.

Ring Counters...
In the diagram above, assuming a starting state of Q3 = 1 and Q2 = Q1
= Q0 = 0. At the first pulse, the 1 shifts from Q3 to Q2 and the counter
is in the 0100 state. The next pulse produces the 0010 state and the third,
0001. At the fourth pulse, the 1 at Q0 is transferred back to Q3, resulting
in the 1000 state, which is the initial state. Subsequent pulses will cause
the sequence to repeat, hence the name ring counter.
The ring counter above functions as a MOD-4 counter since it has four
distinct states and each flip-flop output waveform has a frequency equal to
one-fourth of the clock frequency. A ring counter can be constructed for
any MOD number. A MOD-N ring counter will require N flip-flops
connected in the arrangement as the diagram above.

Ring Counters...

Ring Counters...
A ring counter requires more flip-flops than a binary counter for the same
MOD number. For example, a MOD-8 ring counter requires 8 flip-flops
while a MOD-8 binary counter only requires 3 (23 = 8). So if a ring
counter is less efficient in the use of flip-flops than a binary counter, why
do we still need ring counters? One main reason is because ring counters
are much easier to decode. In fact, ring counters can be decoded without
the use of logic gates. The decoding signal is obtained at the output of its
corresponding flip-flop.

Ring Counters...
A ring counter requires more flip-flops than a binary counter for the same
MOD number. For example, a MOD-8 ring counter requires 8 flip-flops
while a MOD-8 binary counter only requires 3 (23 = 8). So if a ring
counter is less efficient in the use of flip-flops than a binary counter, why
do we still need ring counters? One main reason is because ring counters
are much easier to decode. In fact, ring counters can be decoded without
the use of logic gates. The decoding signal is obtained at the output of its
corresponding flip-flop.
For the ring counter to operate properly, it must start with only one
flip-flop in the 1 state and all the others at 0. Since it is not possible to
expect the counter to come up to this state when power is first applied to
the circuit, it is necessary to preset the counter to the required starting
state before the clock pulses are applied. One way to do this is to apply a
pulse to the PRESET input of one of the flip-flops and the CLEAR inputs
of all the others. This will place a single 1 in the ring counter.

The Johnson counter, also known as the twisted-ring counter, is exactly
the same as the ring counter except that the inverted output of the last
flip-flop is connected to the input of the first flip-flop.

Ring Counters...
Figure : Hohnson counter (Mod -6 Counter)

Ring Counters...

Ring Counters...
The Johnson counter works in the following way : Take the initial state of
the counter to be 000. On the first clock pulse, the inverse of the last
flip-flop will be fed into the first flip-flop, producing the state 100. On the
second clock pulse, since the last flip-flop is still at level 0, another 1 will
be fed into the first flip-flop, giving the state 110. On the third clock
pulse, the state 111 is produced. On the fourth clock pulse, the inverse of
the last flip-flop, now a 0, will be shifted to the first flip-flop, giving the
state 011. On the fifth and sixth clock pulse, using the same reasoning, we
will get the states 001 and 000, which is the initial state again. Hence,
this Johnson counter has six distinct states : 000, 100, 110, 111, 011 and
001, and the sequence is repeated so long as there is input pulse. Thus
this is a MOD-6 Johnson counter.

Ring Counters...

Ring Counters...
The MOD number of a Johnson counter is twice the number of flip-flops.
In the example above, three flip-flops were used to create the MOD-6
Johnson counter. So for a given MOD number, a Johnson counter requires
only half the number of flip-flops needed for a ring counter. However, a
Johnson counter requires decoding gates whereas a ring counter doesnt.
As with the binary counter, one logic gate (AND gate) is required to
decode each state, but with the Johnson counter, each gate requires only
two inputs, regardless of the number of flip-flops in the counter. Note that
we are comparing with the binary counter using the speed up technique
discussed above. The reason for this is that for each state, two of the N
flip-flops used will be in a unique combination of states. In the example
above, the combination Q2 = Q1 = 0 occurs only once in the counting
sequence, at the count of 0. The state 010 does not occur. Thus, an AND
gate with inputs (not Q2) and (not Q2) can be used to decode for this
state. The same characteristic is shared by all the other states in the
sequence.

Thank you
Please send your feedback at nbahadure@gmail.com

Thank you
Please send your feedback at nbahadure@gmail.com
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Digital electronics sequential ckts counters

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