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Overview of ST7 8-bit Microcontrollers

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Overview of ST7 8-bit Microcontrollers and its key features.

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Overview of ST7 8-bit Microcontrollers

  1. 1. Overview of ST7 8-bit Microcontrollers <ul><li>Source: STMicroelectronics </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module provides an overview of ST7 8-bit Microcontrollers and its key features. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>ST7 Portfolio </li></ul></ul><ul><ul><li>Key Applications </li></ul></ul><ul><ul><li>8-Bit μC – General Purpose line </li></ul></ul><ul><ul><li>ST7 CORE Block Diagram </li></ul></ul><ul><ul><li>Introduction to different features </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>29 pages </li></ul></ul>
  3. 3. Introduction to ST7 <ul><li>Mainstream 8 bit microcontroller product line for STMicroelectronics. (MCU division, Automotive, Smart Card...) </li></ul><ul><li>Industry standard 8 bit Core based on CISC architecture, easy hands on. </li></ul><ul><li>Ideal for platform integration , core and peripheral compatibility from 1K to 60K program memory as well as compatible package configuration. RAM Memory: 128 to 5K bytes. </li></ul><ul><li>Recognized for best in class EMC behaviour. </li></ul><ul><li>Flash, ROM and FAST ROM to accommodate production ramp-up and economy of scale. </li></ul><ul><li>From 2.4V to 5V Range in order to support different voltage environments. </li></ul><ul><li>Cost Effective with models in Flash </li></ul><ul><li>High reliability supported by the most demanding quality standards, The best Flash Data-retention specification. </li></ul><ul><li>Complete tools offer </li></ul><ul><ul><li>From low cost development tools up to very high end emulators </li></ul></ul><ul><ul><li>Various demonstration boards, and software library for an quick and easy hands on. </li></ul></ul><ul><ul><li>In Circuit debugging module for fast verification. </li></ul></ul><ul><ul><li>Production tools for Flash including Gang Programmer, or software DLL for ICP. </li></ul></ul><ul><li>Aggressive technology road map down to 0.18um </li></ul>
  4. 4. Features <ul><li>Advanced architecture offering </li></ul><ul><ul><li>Fast Programming and cost effective High Density Flash memory </li></ul></ul><ul><ul><li>Rich Interrupt management </li></ul></ul><ul><ul><li>In-circuit programming </li></ul></ul><ul><ul><li>Data retention robustness </li></ul></ul><ul><li>Rich Peripheral set : </li></ul><ul><ul><li>SCI, LINSCITM, CAN 2.0B, SPI, I²C, USB, 16b timer, 8b timer </li></ul></ul><ul><ul><li>Fast Conversion 10 bit A/D (3us to 7us) </li></ul></ul><ul><ul><li>Wide choice of combination </li></ul></ul><ul><li>Scalable solution </li></ul><ul><ul><li>from Low to high pin count (8 to 80 pins) </li></ul></ul><ul><ul><li>small to large memory (4K to 60K) </li></ul></ul><ul><ul><li>2.7V and 5V Applications, various Power saving modes </li></ul></ul><ul><li>The ST7 core (von neuman architecture) is built around </li></ul><ul><ul><li>An 8-bit Arithmetic and Logic Unit (ALU) </li></ul></ul><ul><ul><li>6 internal registers: Accumulator (A), X and Y index registers, </li></ul></ul><ul><ul><li>Program Counter (PC), the Stack Pointer (SP) and the Code Condition register (CC) </li></ul></ul><ul><ul><li>A controller block </li></ul></ul>
  5. 5. ST7 Portfolio
  6. 6. Key Applications
  7. 7. 8-Bit μC – General Purpose Line Complexity
  8. 8. ST7 CORE Block Diagram ST7 Core
  9. 9. Internal Registers Six Internal Register
  10. 10. The memory space  
  11. 11. ST7 INTERRUPTS Overview <ul><li>Except for the software interrupt (TRAP Instruction), all interrupts can be masked by setting the I BIT in CC </li></ul><ul><li>When an interrupt occurs: </li></ul><ul><ul><li>The context is saved on the stack (CC, A, X, PC) </li></ul></ul><ul><ul><li>All other interrupts are masked (the I bit is set By H/W) </li></ul></ul><ul><ul><li>The interrupt vector is loaded in the Program Counter </li></ul></ul><ul><li>When return from interrupt is executed: </li></ul><ul><ul><li>The original context is automatically restored (CC, A, X, PC) </li></ul></ul><ul><ul><li>Interrupts are enabled (I bit reset) </li></ul></ul><ul><li>Priority between interrupts is given by the interrupt address vector (Higher address = higher priority) </li></ul>Different Interrupts CPU INTERRUPT Reset Trap (Instruction) External Interrupt 0 External Interrupt 1 CSS SPI Timer A Timer B I2C <ul><li>Interrupt vectors: </li></ul>up to 16 vectors <ul><li>Number: </li></ul>16 levels hardwired <ul><li>Software priority (Nested mode only): </li></ul>4 levels user configurable <ul><li>Interrupt Reaction Time: </li></ul>1.250µs to 2.750 µs (end of the current instruction +10 cpu cycles) <ul><li>Automatic register pushed: </li></ul>Program counter, accumulator, CC, X
  12. 12. Main Clock Controller
  13. 13. ST7 CORE Reset sources <ul><li>External reset using reset pin </li></ul><ul><ul><li>Purpose: allow to generate an external reset </li></ul></ul><ul><ul><li>Condition: reset pin pull low </li></ul></ul><ul><li>Power supply dependent reset using LVD </li></ul><ul><ul><li>Purpose: ensure the MCU is in a known state whatever Vcc </li></ul></ul><ul><ul><li>Condition: internal reset when Vcc reaches Vcc min </li></ul></ul><ul><li>Watchdog reset using the watchdog timer </li></ul><ul><ul><li>Purpose: guarantee the safety in case of software trouble </li></ul></ul><ul><ul><li>Condition: internal reset when the WD register is not refreshed </li></ul></ul><ul><li>Illegal opcode </li></ul><ul><ul><li>Purpose: guarantee the safety in case of software trouble </li></ul></ul><ul><ul><li>Condition: internal reset when executing an undefined prebyte or opcode </li></ul></ul>
  14. 14. Low Voltage Detection <ul><li>3 Selectable levels </li></ul><ul><li>Activation Flag </li></ul><ul><li>RESET pin tied to GND </li></ul>
  15. 15. Flash Memory Module <ul><li>XFlash </li></ul><ul><ul><li>Single voltage </li></ul></ul><ul><ul><li>Cycling:10K in program memory, 300K in data e²prom </li></ul></ul><ul><ul><li>Programming method: Byte per byte or parallel (x32) programming with hardware control </li></ul></ul><ul><ul><li>Prog/Erase time: 5ms for 1 to 32Bytes(including erasing) </li></ul></ul><ul><ul><li>Supply conditions: 2.4V ≤ VDD ≤ 5.5V </li></ul></ul><ul><li>HDFlash </li></ul><ul><ul><li>Dual voltage </li></ul></ul><ul><ul><li>Cycling:100 in program memory Emulated Data E²prom </li></ul></ul><ul><ul><li>Programming method: Byte per byte or parallel (x256) programming and sectorized erasing with Embedded Commands </li></ul></ul><ul><ul><li>Byte Prog: 49us, Block programming: 12.5ms-3s </li></ul></ul><ul><ul><li>Sector erasing: 1.5-8.5s. </li></ul></ul><ul><ul><li>Supply conditions: 3.8V ≤ VDD ≤ 5.5V (dedicated low voltage version) 11.4V ≤ VPP ≤ 12.6V </li></ul></ul>XFlash HDFlash
  16. 16. ST7 EEPROM BLOCK DIAGRAM
  17. 17. FLASH PROGRAMMING <ul><li>How to program: </li></ul><ul><li>ICP: allows to PROGRAM or REPROGRAM (Xflash and HDFlash devices) the Program Memory when the micro is soldered on the application board or on an EPB socket. </li></ul><ul><li>IAP: allows to program the whole FLASH memory except sector 0, when the application is running </li></ul>
  18. 18. ICC MODE Communicating with ICC Protocol <ul><li>Dedicated RESET sequence to enter ICC mode </li></ul><ul><li>Real 4 pin ICC protocol </li></ul><ul><li>ICCCLK, ICCDATA, RESET, VSS (and VPP when needed) </li></ul><ul><li>No speed constraint for ST7 or Controller (PC/Tester) </li></ul><ul><li>Minimum hardware needs to connect to a PC parallel port </li></ul><ul><li>Allow ICD emulation and ICT without any other added external HW resources </li></ul><ul><li>Bidirectional communication protocol </li></ul><ul><li>Optimum command base protocol to manage ICP, ICT, ICD </li></ul><ul><li>Commands: Read, Write, Go, Get SP </li></ul>
  19. 19. ST7 I/O PORTs <ul><li>All the I/Os are individually software configurable using 3 different registers: </li></ul><ul><ul><li>DDR: Data Direction </li></ul></ul><ul><ul><li>Register DR: Data Register </li></ul></ul><ul><ul><li>Option Register </li></ul></ul>
  20. 20. ST7 A/D CONVERTER Block diagram <ul><li>8-Bit on ST72254, ST72334, ST7Lite0 3µS </li></ul><ul><li>10-Bit on ST7Lite2, ST72264, ST7232x, ST72521,ST7262 7.25µS </li></ul><ul><li>Conversion based on successive approximations with sample and hold circuitry </li></ul><ul><li>Up to 16 analog channels Conversion time at fADC = 4MHz </li></ul>
  21. 21. ST7 16-BIT Timer Block Diagram
  22. 22. ST7 SPI Block Diagram
  23. 23. ST7 SCI Block Diagram 
  24. 24. ST7 I 2 C Block Diagram I 2 C CLOCK CONTROL REGISTER
  25. 25. ST7 USB Interface <ul><li>Topology: Master-Slave architecture </li></ul><ul><li>Tiered Star Physically    - Up to 6 tiers    - Up to 127 devices    - 1 Master = Host </li></ul><ul><li>Bus transaction </li></ul><ul><ul><li>Speed </li></ul></ul><ul><ul><ul><li>12Mbps (full speed) - 1.5Mbps (low speed) - 480Mbps (High speed) - Embedded clock and data </li></ul></ul></ul><ul><ul><li>Isochronous and Asynchronous transfer  </li></ul></ul>PERFORMANCE APPLICATION ATTRIBUTES LOW SPEED Interactive Devices 10 - 100kb/s Keyboard, Mouse Game peripherals Monitor Configuration Lower cost Hot plugging Ease of use Multiple peripherals Full SPEED Phone, Audio Compressed Video 500Kb/s - 10Mb/s Printers Scanners Telephony Audio Low cost Hot plugging Ease of use Guaranteed latency Guaranteed Bandwidth Multiple devices HIGH SPEED (USB 2.0) Video, Disk 25 - 500 Mb/s Video Mass Storage High Bandwidth Guaranteed latency Ease of use
  26. 26. USB Host / Device <ul><li>LOW SPEED USB: </li></ul><ul><li>The ST7263B series USB devices used in applications such as game pads, joysticks and UPS devices that need to exchange only short messages with the host computer. </li></ul><ul><li>Benefit of low-speed USB: 3 endpoints including 2 with interrupt IN/OUT capability. </li></ul><ul><li>HIGH SPEED USB: </li></ul><ul><li>The ST7SCR provides low pin-count and single-chip solutions for EMV smartcard readers, with an exceptionally high level of integration. It includes an integrated smartcard analog interface and UART. </li></ul><ul><li>Benefit of full-speed USB: 5 endpoints including 3 with interrupt IN/OUT and bulk capability </li></ul>
  27. 27. Basic vs. Full CAN <ul><li>Full CAN controller </li></ul><ul><li>Many Buffer </li></ul><ul><li>Sophisticated message filtering </li></ul><ul><li>Dedicated HW </li></ul><ul><li>Larger silicon (buffer size, filtering) </li></ul><ul><li>Buffer allocation is static based on message ID </li></ul><ul><li>Messages may not be copied to RAM (automatic reply capability) </li></ul><ul><li>Typical: Car body </li></ul><ul><li>Basic CAN </li></ul><ul><li>Few Tx/Rx buffers </li></ul><ul><li>Simple identifier filtering </li></ul><ul><li>More SW overhead </li></ul><ul><li>Less silicon </li></ul><ul><li>Buffer allocation is dynamic based on avalaibility </li></ul><ul><li>Messages must be copied to RAM (more CPU load) Typical: Engine management </li></ul>
  28. 28. ST7 CAN CELL - Block Diagram
  29. 29. Additional Resource <ul><li>For ordering the ST7 Microcontrollers, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.st.com/mcu/inchtml-pages-st7.html </li></ul></ul>Newark Farnell

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