1. Jayachandra Vudumula
E-mail : jayachandra.vudumula@gmail.com
Mobile : +91-8884445613
Objective: To be a part of organization that provides an atmosphere of mutual growth and benefits, where
I can contribute my skills and experience.
Career summary:
• Working as an RTL design Engineer in HCL Technologies, Bangalore.
• Over all experience of 3 years in VLSI Front-end design.
• Experience in developing block level design and Integration of IP’s using Verilog and VHDL.
• Expertise in developing Ethernet MAC (RMII, SMII, MII).
• Expertise in developing L2 layer IP blocks for network protocols like GFP, HDLC, E1, Ethernet
(MAC), PDH, SDH networks.
• Expertise in developing SRAM, SPI, UART and interface protocols.
• Experience of real time debugging using Techtronics digital oscilloscope.
• Experience of real time debugging using JTAG Debug tools in Quartus.
• FPGA design flow from RTL design to Altera Quartus tool flow.
• Knowledge on AMBA AHB & AMBA APB and DDR.
• Knowledge on TCP/IP OSI layer protocols.
Core Skills:
• Languages : VHDL, Verilog HDL, C.
• Simulators : modelsim
• FPGA Tools : Altera - Quartus II IDE.
• FPGA devices : Altera - Cyclone IV E family
• Protocols : Ethernet RMII, SMII, MII, SPI, UART and AMBA.
• Ethernet Testing tool : Wire shark.
• Testing : Experience with JTAG logic analyzers, Tektronics Oscilloscope.
• Operating systems : Linux, windows xp, windows 7.
Educational summary:
• M Sc Electronics & Communications in Sri Krishna Devaraya University, Anantapur with 79%.
• B Sc Electronics in Sreenivasa Degree College, Dharmavaram with 83%.
• Intermediate in Govt. junior college, Dharmavaram with 83%.

2. • SSC in SPCS municipal high school, Dharmavaram with 83%.
IP's Developed:
1. Name : GFP (Generic Framing Procedure)
Role : RTL design engineer
Description : It is a multiplexing procedure as per ITU-T G.7041. Mapping variable is length
Client signals over TDM signals. Here GFP-F framing procedure developed and
Mapping Ethernet packets of different lengths into GFP frames.
Design blocks : GFP-F TX-framer, Rx-framer
CRC-32, CRC-16 generator
Scrambler, descrambler.
2. Name : Ethernet MAC using DMA controlling process.
Role : RTL design engineer
Description : Developed as per IEEE 802.3 and IEEE 802.1Q standards in MII, RMII and SMII
modes. In this receiving and validating each Ethernet packet based on Hardware
address, IP address, type of packet and CRC check sum calculation. If the receiving
packet satisfy all these conditions then the packet is sending to processor using
circular buffer descriptors concept.
Design blocks : Ethernet Rx, Ethernet TX
CRC Generator and checker
Interrupt Generation
Projects:
1. Name : NOMUS Gateway e E1/V.35
Role : RTL design engineer
IP's included : E1-Framer, Digital PLL
Description : This project is about Plesio-synchronous Digital Hierarchy (PDH) as per ITU-T G.703
standard, transmit the data long distance through SHDSL. Data is checking and
validating by CRC-4 polynomial. This product is working in two modes,
1. E1 mode
2. V35 mode
E1 is always working on 2 M bps and V.35 interface supports Nx64 data rates. Nx64
clocks are generated by digital PLL. This project supports maximum of 2Mbps on 2-
wire and 4 M bps on 4-wire channels.
Design blocks : E1- Framer, E1_Deframer
CRC-4 Generator & Checker
Digital PLL.

3. 2. Name : NOMUS Gwe-ES
Role : RTL design engineer
IP's included : VCAT-LCAS, GFP
Description : This project is about transmission of Ethernet data over 2 DSL (Digital Subscriber
Line) lines. Ethernet data is mapped into GFP-F and distributed between 2 DSL lines
using VCAT-LCAS protocol.
Design blocks : Data mapper & de-mapper according to time slot configuration.
Data multiplexing logic's.
3. Name : NOMUS GW e RB Static Router
Role : RTL design engineer
IPs included : HDLC, ETHERNET MAC and Maintaining MAC and IP tables.
Description : This project about routing of Ethernet packets on different networks. This product is
working on two modes namely,
1. Router
2. Bridge
Ethernet packets are mapped into HDLC and transmitting through SHDSL and de-
mapping the packets, packet validation and ERROR detection is performing with
CRC-16 through the IPv4 header. Routing process done by maintaining static
routing table and MAC tables. Maintaining ROUTING table and Dynamic MAC tables.
Key blocks : CRC-16 calculation and insertion for IPv4 header
Error detection, packet validation
Transmitting data through HDLC blocks.
Personal details:
Date of birth : 16th
march 1991
Gender : male
Nationality : Indian
Marital Status : single
Temporary address : Venkateswara layout, Madiwala, BTM 1st
stage,
Bangalore – 560068.
Permanent address : H.no: 28-267, Rajendra Nagar, Dharmavaram,
Anantapur district, Andhra Pradesh - 515671.
- Jayachandra vudumula