The document proposes a novel VLSI DHT algorithm that is well suited for highly parallel and modular architecture. It can efficiently split the DHT algorithm into several parallel parts that can be executed concurrently, reducing hardware complexity. The algorithm extensively uses subexpression sharing techniques and sharing of common multipliers, which helps achieve high parallelism and reusability of hardware. The outcomes expected are a low complexity VLSI implementation of the length-N DHT with a modular structure, reduced hardware needs through subexpression sharing, and efficient sharing of multipliers.

1. A Novel VLSI DHT Algorithm for a Highly
Modular and Parallel Architecture
NO: 6, 11th Main, Jaya nagar 4th Block, Bangalore-560011
9611582234, 9945657526
Abstract
The DHT algorithm can be efficiently split on several parallel parts that can be executed
concurrently. Moreover, the proposed algorithm is well suited for the subexpression sharing
technique that can be used to significantly reduce the hardware complexity of the highly
parallel VLSI implementation and also share multipliers efficiently.
Introduction
The Discrete Fourier transform (DFT) is used in many digital signal processing applications
as in signal and image compression techniques, filter banks, signal representation, or
harmonic analysis. The discrete Hartley transform (DHT) can be used to efficiently replace
the DFT when the input sequence is real Since DHT is computationally intensive, it is
necessary to derive dedicated hardware implementations using the VLSI technology
Objective
VLSI DHT algorithm that is well suited for a VLSI implementation on a highly parallel and
modular architecture is proposed. Achieving high modular helps in achieve parallelism. Share
the hardware which improve the hard ware reusability
Research Method

2. NO: 6, 11th Main, Jaya nagar 4th Block, Bangalore-560011
9611582234, 9945657526
Possible outcome
 To design and implement highly parallel VLSI algorithm for the computation of a
length-N = 2n DHT having a modular and regular structure has been presented.
 Deign should be a low hardware complexity by extensively using a subexpression
sharing technique and the sharing of multipliers having the same constant.
 Efficient sharing of multipliers (reduces in numbers multipliers needed)