VLSI Projects in Bangalore 9611582234, 9945657526

1. FPGA implementation of Truncated Multiplier for Array multiplication
Introduction
N eminence multiplier is always being a need of electronics industry for applications in DSP,
image processing. A truncated multiplier is a p × p multiplier with p bits output. In a
truncated multiplier the p less significant bits of the full-width product are discarded to
compensate it some of the partial products are removed and replaced by a suit- able
compensation function, to trade-off accuracy with hardware cost. A system’s performance is
generally depending on the performance of the multiplier because the multiplier operation is
time consuming which makes it slowest clement in the system. Moreover, it is generally the
large area consuming. That's why; optimizing both the speed and area of the multiplier is a
key design issue. Conversely, area and speed are usually conflicting constraints so that
improving one result in affecting other. Most algorithms involve a shift and an add technique
where the multiplicand is conditionally added to obtain the final result. Although there are
many algorithms for accomplishing this, there is no reduction in the height of partial products
that need to be summed to produce the final result.
Proposed project work
Most existing schemes target both array and tree multipliers. The design of high-speed, area-efficient
multipliers is essential for VLSI implementations of digital signal processing
systems. Use of truncations schemes gives significant reduction in complexities of design.
Truncation is best suited where exact result is not always required and a rounded product is
used for further computation
1. The existing truncated multiple consumes more area, by exploiting the symmetry of the
multiplexer based array multiplier, the partial product bits generated by the multiplexers in
our truncated multiplier can be accumulated in a carry-save format to further reduce the area
and improve the speed over other truncated array multipliers
2. To minimize the truncation error for an unsigned integer multiplication, a new pseudo-carry
compensated truncation (PCT) scheme consisting of an adaptive compensation circuit
and a fixed bias is proposed
NO: 6, 11th Main, JAYA NAGAR 4TH BLOCK, BANGALORE-560011
9611582234, 9945657526

2. HARDWARE REQUIREMENTS
 Xilinx Spartan 6 or 3 FPGA development board
 Other peripherals
SOFTWARE REQUIREMENTS
 Xilinx ISE 13.2
 Verilog HDL
Possible outcome
 The proposed truncated multiplier will consume less power compared to existing
truncated multiplier
 The truncation error efficiency will be improved
 The proposed truncated multiplier will occupy less area compared to the existing
truncated multiplier
 We will also try to reduce the propagation delay.
NO: 6, 11th Main, JAYA NAGAR 4TH BLOCK, BANGALORE-560011
9611582234, 9945657526