1. Himanshu Sharma
121 N 8TH Street Apt # 2 himanshu.uiet@gmail.com
San Jose 95112 (408)834-9925
Objective Seeking a challenging and engaging full-time opportunity in the semiconductor industry.
Education M.S. in Electrical engineering
San José State University, San José, CA December 2010
B.E. in Electronics and Communication May 2006
Panjab University, Chandigarh, India
Hardware Description Language: Verilog
Skills EDA Tools: Cadence® ICFB (Including Cadence® Front End Virtuoso and Cadence® Assura
Physical verification ), Cadence® SoC Encounter , Xilinx® ISE, ModelSim PE, Cadence® NC SIM, PCB
designing using OrCAD 9.1, Matlab, U-link/Keil.
Lab Equipment: Oscilloscope, Spectrum analyzer, Temperature forcing system, National
instruments, Sourcemeter, Waveform generator, Microscope, PCB assembly.
Professional NXP Semiconductors, San jose, CA
Experience Analog Circuit Design intern, September 2010 – Present
Testing and characterizing analog IP on schematic, analog test chip and on the microcontroller
product. Working with the designers to debug and investigate circuit issues found on the bench.
Product validation to ensure the chip meets specifications prior to customer release. Tasks
accomplished:
 Amplifier characterization: Distortion analysis (THD vs Vcm, THD vs Supply, THD vs Input
voltage, THD vs Loading), Noise analysis, voltage gain variations with load and supply
voltage, settling time.
 Band gap Reference: Startup testing, settling time and power measurements
 Power Management Unit: Startup testing, Power Measurements in different modes,
loading characterization.
 BOD: Simulation and bench characterization
 Crystal oscillator: RTC Reset Disturb test, duty Cycle variations, jitter measurements.
 IRC oscillator: frequency measurements, drift analysis.
San Jose State University, San Jose, CA
Teaching Associate, January 2009- May 2009
Instructing Digital Design Lab to Undergraduate students, assist them with their projects and
evaluate their performance on the basis of their assignments and projects.
Eon Infotech Ltd (VEDANT, Semi-Conductor Laboratories), Mohali, India
Design Engineer, April 2007 – January 2008
Designing, simulation, Layout and testing of design problems individually or as a member of a
team; supervising the industrial trainees with their project work and introducing them to the
working of various EDA tools

2. Academic 32-Bit ALU: Designed, simulated and laid out a 32-bit, 2Ghz Arithmetic Logic Unit using dynamic
Projects CMOS logic. Tools used: Cadence ICFB
PLL Design: Designed, simulated and laid out a 2GHz Phase Locked loop in GPDK 45nm
technology.Tools Used: Cadence 6.1
SRAM Design: Designing, simulation and layout of SRAM cell. Performed DRC & LVS clean layout
and did RC Extraction. Tools used- Cadence ICFB (Front end Virtuoso and Back end Assura).
Op-Amp Design: Designed, simulated and laid out a two stage Op-amp according to the
given specifications. Tools used: Cadence ICFB
2-D Graphics Filter: Basic image processing for a video image of 240 x 160 pixels. The task
involved designing the architecture and writing, simulating and synthesizing the Verilog HDL code.
Tools used: ModelSim PE and Xilinx ISE.
Himanshu Sharma