The document provides a summary of Darrell J Hubbard's experience as an IC Mask Layout Designer including over 30 years of experience in mask layout design. It lists his areas of expertise in techniques like transistor matching and guard rings. It also provides his work history with companies like Qualcomm, Microchip Technology, ZILOG, and American Microelectronics Inc where he has designed circuits like memory, DRAM, SRAM and more. It includes his education and skills in tools like Cadence layout tools.

1. SR. LAYOUT MASK DESIGNER
Darrell J Hubbard
3808 Vista Campana #6
Oceanside CA, 92057
Home Phone (208) 840-0026
Mobile Phone (208) 840-0026
darrell.hubbard1@gmail.com
IC Mask Layout Designer,
30+ years experience in mask layout design
Experienced in RF, Analog, SERDES, Memory, Digital Design Techniques including;
transistor matching, pairing, common centroid, balanced symmetrical, device
matching, guard rings, and noise shielding.
Proficient in chip floorplanning, cell placement, block placement, powerbus
arrangement and multiple metal options.
Experienced with 10nm finfet, 14nm, 16nm, 20nm, 28nm, 45nm, 65nm and up.
Experienced in RF analog, Custom analog mixed-signal layout experience in the
following: complex logics, sense amps, Data Latch, Flip-Flop, Shift Register,
Regulators, Band Gap, XY decoders, Charge Pump, OPAMP, SRAMs, Bias, PLL, DAC, ADC,
buffers (tristate buffer, output buffer, input buffer), Clock Generators, ESD’s,
I/O devices
Work History
Qualcomm | San Diego California August 2010 - Present
Senior Mask Layout Designer
Analog, RF, Memories, SERDES circuits for a high profile project, working with
engineers to meet their requirements for high speed and other critical
requirements. Working with Cadence XL, assuring clean DRC, ERC, and LVS extracting
parasitic for engineering simulations. Working in 10nmFinFet and up to 65nm
processes.
Microchip Technology | Tempe Arizona January 2002 - August 2009
Lead Layout Designer with the Technology Development group. Layout and generate
test structures for new process and technologies. Designing Memory, DRAM & SRAM.
Assure proper layout procedures, meeting engineering requirements for speed &
current. Verify designs and getting extracted information back to Engineers for
simulations. Work with engineering evaluate design rules for production design
groups. Generate new macros, P cells, and test vehicles for new processes. Take
lead in assigned projects, bringing all the data together to build circuits for
customer and get to production.
ZILOG | Nampa, Idaho November 1991 - January 2002
Senior Layout Mask Designer engineer for ASIC group. Work with design engineers to
layout full custom circuit and chips. Assign layout support for bocks and macros,
top level chip assembly with cadence place and route tools. Closely work with
design engineers with P&R results to achieve desired results Verify and generate
related documentation for each design. Prepare product for fabrication.
Working as member of the ESD team.

2. American Microelectronics Inc. | Pocatello, ID May 1983 - November 1991
IC Layout Designer
Layout designer
Full custom layout design of chips from micro processors, sensors, gate arrays. All
chips build for local fabrication. Using in house tools. Moving to cadence tools as
process evolve. Active in each chip until release to production.
USMC 1978-1982
EDUCATION
Preston Senior High School Graduate
Idaho State University no degree
SKILLS
Unix based computer Intermediate, Cadence layout tools Expert, Solid Works 3D CAD
Beginner, Hercules,Cadence, and Asura verification tools Experienced user.
LANGUAGES
English