The memory cycle times have been much longer than processor cycle times; this speed gap between the memory and the processor means that the processor must wait for memory to respond to an access request. The obvious method of increasing the speed of the memory system is by using a higher speed memory technology. Once the technology is selected, the access speeds can be increased further by different address decoding and access techniques. Described in details at least 3 of them Solution The different techniques are: 1. Banking: The main memory is built out of several physical-memory modules. Each and every module is a memory bank of a certain capacity and consists of a MAR and a MBR. In semiconductor memories, each module corresponds to either a memory IC or a memory board consisting of several memory ICs. The consecutive addresses lie in the same bank. If each bank contains 2n = N words and if there are 2m = M banks in the memor y, then the system MAR would contain n + m bits. 2. Multiport Memories: Multiple memories are available in which each port corresponds to an MAR and an MBR . Independent access to the memory can be made from each port. The memory system resolves the conflicts between the ports on a priority basis. Multiport memories are useful in an environment where more than one device accesses the memory. Examples of such systems are a single-processor system with a direct-memory access (DMA), I =O controller, and a multiprocessor system with more than one CPU. 3.Instruction Buffer: The instruction buffer, Providing a first-in, first-out (FIFO) buffer between the CPU and the primary memory enhances the instruction fetch speed . Instructions from the primary memory are fed into the buffer at one end and the CPU fetches the instructions from the other end. As long as the instruction execution is sequential, the two operations of filling the buffer and fetching from the buffer into CPU can go on simultaneously. But when a jump (conditional or unconditional) instruction is executed, the next instruction to be executed may or may not be in the buffer. The buffer management requires hardware component to manage the queue and mechanisms to identify the address range in the buffer and to freeze and unfreeze the buffer. INTEL 8086 processor uses a 6 -byte long instruction buffer organized as a queue. CDC 6600 uses an instruction buffer that can store eight 60-bit words, that is, 16–32 instructions, since the instructions are either 15- or 30-bits long..

1. The memory cycle times have been much longer than processor cycle times; this speed gap
between the memory and the processor means that the processor must wait for memory to
respond to an access request. The obvious method of increasing the speed of the memory system
is by using a higher speed memory technology. Once the technology is selected, the access
speeds can be increased further by different address decoding and access techniques. Described
in details at least 3 of them
Solution
The different techniques are:
1. Banking: The main memory is built out of several physical-memory modules. Each and every
module is a memory bank of a certain capacity and consists of a MAR and a MBR. In
semiconductor memories, each module corresponds to either a memory IC or a memory board
consisting of several memory ICs. The consecutive addresses lie in the same bank. If each bank
contains 2n = N words and if there are 2m = M banks in the memor y, then the system MAR
would contain n + m bits.
2. Multiport Memories: Multiple memories are available in which each port corresponds to an
MAR and an MBR . Independent access to the memory can be made from each port. The
memory system resolves the conflicts between the ports on a priority basis. Multiport memories
are useful in an environment where more than one device accesses the memory. Examples of
such systems are a single-processor system with a direct-memory access (DMA), I =O controller,
and a multiprocessor system with more than one CPU.
3.Instruction Buffer: The instruction buffer, Providing a first-in, first-out (FIFO) buffer between
the CPU and the primary memory enhances the instruction fetch speed . Instructions from the
primary memory are fed into the buffer at one end and the CPU fetches the instructions from the
other end. As long as the instruction execution is sequential, the two operations of filling the
buffer and fetching from the buffer into CPU can go on simultaneously. But when a jump
(conditional or unconditional) instruction is executed, the next instruction to be executed may or
may not be in the buffer. The buffer management requires hardware component to manage the
queue and mechanisms to identify the address range in the buffer and to freeze and unfreeze the
buffer. INTEL 8086 processor uses a 6 -byte long instruction buffer organized as a queue. CDC
6600 uses an instruction buffer that can store eight 60-bit words, that is, 16–32 instructions, since
the instructions are either 15- or 30-bits long.