1. 1. A 32-bit addressbusallowsaccessto a memoryof capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb
2. Which processorstructure ispipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
3. In 8086 microprocessorone of the followingstatementsisnottrue.
A ) CoprocessorisinterfacedinMAXmode
b) CoprocessorisinterfacedinMIN mode
c)I/Ocan be interfacedinMAX/ MIN mode
d)Supportspipelining
4. The ________ ensuresthatonlyone ICis active at a time to avoida busconflictcausedbytwo ICs
writingdifferentdatatothe same bus.
A. control bus B. control instructions C. addressdecoder D.CPU
5. In an 8085 microprocessor,the instructionCMPB has beenexecutedwhilethe contents of
accumulatorislessthan that of registerB.As a resultcarry flagand zeroflagwill be respectively
(A) set,reset (B) reset,set(C) reset,reset(D) set,set
6. To put8085 microprocessorinthe waitstate
(a) lowerthe READY input B. ) raise the HOLD input (C) raise the READY input
7. Registers,whichare partiallyvisible tousersandusedtoholdconditional,are knownas
A. PC b. Memoryaddressregisters c. General purpose register d. Flags
8. What type of control pinsare neededinamicroprocessortoregulate trafficonthe bus,in orderto
preventtwodevicesfromtryingtouse itat the same time? A. Bus control b. Interrupts
c. Bus arbitration d. Status
9. Who inventedthe microprocessor? a. Marcian E Huff b.Herman H Goldstein
c. JosephJacquard d.All of above
10. Before amodemtransmits,itsenda: a. CTS b. DTR c. DSR d. RTS
11. The numberof memorycyclesrequiredtoexecute the following8085 instructions
(i) LDA 3000H
( ii) LXID, FOF1H wouldbe
(A) 2 for (i) and2 for (ii)
(B) 4 for (i) and2 for (ii)
(C)3for (i) and3 for (ii)
(D)3 for(i) and 4 for (ii)
12.The 8255 Programmable Peripheral Interface is usedasdescribedbelow.
(i) AnA/Dconverterisinterfacedtoa microprocessorthroughan8255. The conversionisinitiated
by a signal fromthe 8255 on Port C.A signal onPort C causesdata to be stobedintoPortA.
(ii) Twocomputersexchangedatausinga pairof 8255s.Port A worksas a bidirectional dataport
supportedby appropriate handshakingsignals.The appropriate modesof operationof the 8255 for(i)
and (ii) wouldbe
(A)Mode 0 for(i) and Mode 1 for (ii)
(B)Mode 1 for (i) andMode 2 for(ii)
(C)Mode 2 for (i) andMode 0 for (ii)
(D) Mode 2 for (i) andMode 1 for (ii)
13. The microprocessor8085 has _____ basicinstructionsand_____ opcodes
a) 80, 246 b) 70, 346 c) 80, 346 d) 70, 246
14. What doesmicroprocessorspeeddependson a) Clock b) Data bus width
c) Addressbuswidth d)Size of register
15. The status that cannotbe operatedbydirectinstructionsis a) Cy b) Z c) P d) AC
