mcq

1. UNIT-4
PIPELINE PROCESSING AND MEMORY ORGANISATION
1.The pipelining process is also called as ______
a) Superscalar operation
b) Assembly line operation
c) Von Neumann cycle
d) Processor
Answer:b
2.The fetch and execution cycles are interleaved with the help of ________
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit
Answer:b
3.Each stage in pipelining should be completed within ___________ cycle.
a) 1
b) 2
c) 3
d) 4
Answer:a
4.To increase the speed of memory access in pipelining, we make use of _______
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
Answer:c
5.The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
Answer:a
6. A collection of lines that connects several devices is called ..............

2. a) bus
b) peripheral connection wires
c) Both a and b
d) internal wires
Answer:a
7. PC Program Counter is also called ...................
a) instruction pointer
b) memory pointer
c) data counter
d) file pointer
Answer:a
8. When a subroutine is called, the address of the instruction following the CALL instructions
stored in/on the
a) stack pointer
b) accumulator
c) program counter
d) Stack
Answer: d
9. From where interrupts are generated?
a) Central processing unit
b) Memory chips
c) Registers
d) I/O devices
Answer: d
10. Systems that do not have parallel processing capabilities are
a) SISD
b) SIMD
c) MIMD
d) MISD
Answer: a

3. 11. How many address lines are needed to address each memory location in a 2048X 4 memory
chip?
a) 10
b) 11
c) 8
d) 12
Answer: b
12. Parallel processing may occur
a) in the instruction stream
b) in the data stream
c) instruction and data stream
d) fetch and decode
Answer:c
13. Characteristic of RISC (Reduced Instruction Set Computer) instruction set is
a) three instructions per cycle
b) two instructions per cycle
c) one instruction per cycle
d) four instruction per cycle
Answer:c
14. In daisy-chaining priority method, all the devices that can request an interrupt are connected
in
a) parallel
b) serial
c) random
d) balanced
Answer: b
15.In the memory hierarchy,the fastest memory is
a) SRAM
b) Cache
c) Registers
d) DRAM

4. Answer:c
16.Cache memory is implemented using
a) Dynamic RAM
b) Static RAM
c) PROM
d) EROM
Answer:b
17.Given a 256*4 RAM chips,howmany chips are required to provide a memory capacity of
1KB of RAM?
a) 1
b) 8
c) 4
d) 6
Answer:a
18. The standard SRAM chips are costly as _________
a) They use highly advanced micro-electronic devices
b) They house 6 transistor per chip
c) They require specially designed PCB’s
d) 4 chips
Answer:b
19. The next level of memory hierarchy after the L2 cache is _______
a) Secondary storage
b) TLB
c) Main memory
d) Register
Answer:d
20. The last on the hierarchy scale of memory devices is ______
a) Main memory
b) Secondary memory

5. c) TLB
d) Flash drives
Answer:b
21. The effectiveness of the cache memory is based on the property of ________
a) Locality of reference
b) Memory localisation
c) Memory size
d) None of the mentioned
Answer:a
22. The correspondence between the main memory blocks and those in the cache is given by
_________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
Answer:b
23.Memory unit accessed by content is called
a.Read only memory
b.Programmable memory
c.Virtual Memory
d.Associative memory
Answer:d
24. Because of virtual memory, the memory can be shared among ____________
a) processes
b) threads
c) instructions
d) segments
Answer:a
25. Effective access time is directly proportional to ____________
a) page-fault rate

6. b) hit ratio
c) memory access time
d) execution time
Answer:a
26. The algorithm to remove and place new contents into the cache is called _______
a) FIFO algorithm
b) Renewal algorithm
c) Updation
d) Replacement algorithm
Answer:d
27. The memory unit that communicates directly within the CPU, Auxillary memory and
Cache memory, is called
a) Auxiliary Memory
b) Main Memory
c) Registers
d)Virtual Memory
Answer:b
28. A certain processor uses a fully associative cache of size 16KB.The cache block size is
16bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many
bits are required for the Tag and the Index fields respectively in the addresses generated by the
processor?
a) 24bits and 0 bits
b) 28bits and 4 bits
c) 24bits and 4 bits
d) 28bits and 0 bits
Answer:d
29. A cache memory unit with capacity of N words and block size of B words is to be designed.
If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit
is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

7. a) 14.0 to 14.0
b) 15.0 to 15.0
c) 14.0 to 16.0
d) 16.0 to 14.0
Answer:a
30. In designing a computer’s cache system, the cache block (or cache line) size is an important
parameter. Which one of the following statements is correct in this context?
a) A smaller block size implies better spatial locality
b)A smaller block size implies a smaller cache tag and hence lower cache tag overhead
c) A smaller block size implies a larger cache tag and hence lower cache hit time
d) A smaller block size incurs a lower cache miss penalty
Answer:d
31. A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4
decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
a) 4
b) 5
c) 6
d) 7
Answer:b
32. Register renaming is done in pipelined processors
a) as an alternative to register allocation at compile time
b) for efficient access to function parameters and local variables
c) to handle certain kinds of hazards

8. d) as part of address translation
Answer:c
33. A computer has a 256 KByte, 4-way set associative, write back data cache with block size of
32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory
entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.The
size of the cache tag directory is
a) 160K bits
b) 136K bits
c) 40K bits
d) 32K bits
Answer:a
34. For a magnetic disk with concentric circular tracks, the seek latency is not linearly
proportional to the seek distance due to
a) non-uniform distribution of requests
b) arm starting and stopping inertia
c) higher capacity of tracks on the periphery of the platter
d) use of unfair arm scheduling policies
Answer:b
35. In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside
Buffer) can be accessed is
a) Before effective address calculation has started
b) During effective address calculation
c) After effective address calculation has completed
d) After data cache lookup has completed

9. Answer:b
36. Consider a pipelined processor with the following four stages:
IF:InstructionFetch
ID:InstructionDecodeandOperandFetch
EX:Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of
clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1
clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding
is used in the pipelined processor. What is the number of clock cycles taken to complete the
following sequence of instructions?
ADD R2, R1, R0R2 ←← R1 + R0
MUL R4, R3, R2 R4 ←← R3 * R2
SUB R6, R5, R4 R6 ←← R5 - R4
a)7
b)8
c)10
d)14
Answer:b
37. If a unit completes its task before the allotted time period, then _______
a)It’ll perform some other task in the remaining time
b)Its time gets reallocated to a different task
c)It’ll remain idle for the remaining time
d) None of the mentioned
Answer:c
38. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard

10. Answer:a
39. The computer architecture aimed at reducing the time of execution of instructions is
________
a) CISC
b) RISC
c) ISA
d) ANNA
Answer:b
40. The time lost due to the branch instruction is often referred to as ____________
a) Latency
b) Delay
c) Branch penalty
d) Branch lost
Answer:c