Mj 3 Dvlsi


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Mj 3 Dvlsi

  1. 1. Three-dimensional VLSI Matthew Johnson Seminar: Engineering Frontiers March 7, 2001
  2. 2. Contents <ul><li>Traditional (2D) VLSI </li></ul><ul><ul><li>origins </li></ul></ul><ul><ul><li>scientific background </li></ul></ul><ul><ul><li>manufacturing process </li></ul></ul><ul><li>3D VLSI </li></ul><ul><ul><li>origins </li></ul></ul><ul><ul><li>advantages over 2D VLSI </li></ul></ul><ul><ul><li>challenges </li></ul></ul><ul><ul><li>solutions </li></ul></ul>
  3. 3. Contents <ul><li>Influential participants </li></ul><ul><li>Marketing information </li></ul><ul><li>Impact </li></ul><ul><ul><li>societal </li></ul></ul><ul><ul><li>semiconductor industry </li></ul></ul>
  4. 4. VLSI <ul><li>Very Large Scale Integration </li></ul><ul><ul><li>design/manufacturing of extremely small, complex circuitry using modified semiconductor material </li></ul></ul><ul><ul><li>integrated circuit (IC) may contain millions of transistors, each a few  m in size </li></ul></ul><ul><ul><li>applications wide ranging: most electronic logic devices </li></ul></ul>
  5. 5. Origins of VLSI <ul><li>Much development motivated by WWII need for improved electronics, especially for radar </li></ul><ul><li>1940 - Russell Ohl (Bell Laboratories) - first p-n junction </li></ul><ul><li>1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - first transistor </li></ul><ul><ul><li>1956 Nobel Physics Prize </li></ul></ul><ul><li>Late 1950s - purification of Si advances to acceptable levels for use in electronics </li></ul><ul><li>1958 - Seymour Cray (Control Data Corporation) - first transistorized computer - CDC 1604 </li></ul>
  6. 6. Origins of VLSI <ul><li>1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components on 9 mm 2 </li></ul><ul><li>1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated circuit </li></ul><ul><li>1968 - Noyce, Gordon E. Moore found Intel </li></ul><ul><li>1971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300 transistors on 9 mm 2 </li></ul><ul><li>Since then - continued improvement in technology has allowed for increased performance as predicted by Moore’s Law </li></ul>
  7. 7. Moore’s Law <ul><li>Gordon E. Moore - Chairman Emeritus of Intel Corporation </li></ul><ul><li>1965 - observed trends in industry - number of transistors on ICs vs. release dates </li></ul><ul><ul><li>Noticed number of transistors doubling with release of each new IC generation </li></ul></ul><ul><ul><li>release dates (separate generations) were all 18-24 months apart </li></ul></ul><ul><li>Moore’s Law - The number of transistors on an integrated circuit will double every 18 months </li></ul><ul><li>Semiconductor industry has followed this prediction with surprising accuracy </li></ul>
  8. 8. Moore’s Law <ul><li>From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond </li></ul>Relative sizes of ICs in graph
  9. 9. Limits of Moore’s Law? <ul><li>Growth expected until 30 nm gate length (currently: 180 nm) </li></ul><ul><ul><li>size halved every 18 mos. - reached in </li></ul></ul><ul><li>2001 + 1.5 log 2 ((180/30) 2 ) = 2009 </li></ul><ul><ul><li>what then? </li></ul></ul><ul><li>Paradigm shift needed in fabrication process </li></ul>
  10. 10. Scientific principles <ul><li>Semiconductors </li></ul><ul><li>Crystalline solids </li></ul><ul><li>Impurities </li></ul><ul><ul><li>element groups </li></ul></ul><ul><ul><li>n-type material </li></ul></ul><ul><ul><li>p-type material </li></ul></ul><ul><li>p-n junctions </li></ul>
  11. 11. Semiconductors <ul><li>A material whose properties are such that it is not quite a conductor, not quite an insulator </li></ul><ul><li>Some common semiconductors </li></ul><ul><ul><li>elemental </li></ul></ul><ul><ul><ul><li>Si - Silicon (most common) </li></ul></ul></ul><ul><ul><ul><li>Ge - Germanium </li></ul></ul></ul><ul><ul><li>compound </li></ul></ul><ul><ul><ul><li>GaAs - Gallium arsenide </li></ul></ul></ul><ul><ul><ul><li>GaP - Gallium phosphide </li></ul></ul></ul><ul><ul><ul><li>AlAs - Aluminum arsenide </li></ul></ul></ul><ul><ul><ul><li>AlP - Aluminum phosphide </li></ul></ul></ul><ul><ul><ul><li>InP - Indium Phosphide </li></ul></ul></ul>
  12. 12. Crystalline Solids <ul><li>“ In a crystalline solid, the periodic arrangement of atoms… is repeated over the entire crystal.” [Bhatt] </li></ul><ul><li>Silicon crystal - “diamond lattice” </li></ul>
  13. 13. Impurities <ul><li>Silicon crystal in pure form is good insulator - all electrons are bonded to silicon atom </li></ul><ul><li>Replacement of Si atoms can alter electrical properties of semiconductor </li></ul><ul><li>Group number - indicates number of electrons in valence level (Si - Group IV) </li></ul>
  14. 14. Impurities <ul><li>Replace Si atom in crystal with Group V atom </li></ul><ul><ul><li>substitution of 5 electrons for 4 electrons in outer shell </li></ul></ul><ul><ul><li>extra electron not needed for crystal bonding structure </li></ul></ul><ul><ul><ul><li>can move to other areas of semiconductor </li></ul></ul></ul><ul><ul><ul><li>current flows more easily - resistivity decreases </li></ul></ul></ul><ul><ul><ul><li>many extra electrons --> “donor” or n-type material </li></ul></ul></ul><ul><li>Replace Si atom with Group III atom </li></ul><ul><ul><li>substitution of 3 electrons for 4 electrons </li></ul></ul><ul><ul><li>extra electron now needed for crystal bonding structure </li></ul></ul><ul><ul><ul><li>“ hole” created (missing electron) </li></ul></ul></ul><ul><ul><ul><li>hole can move to other areas of semiconductor if electrons continually fill holes </li></ul></ul></ul><ul><ul><ul><li>again, current flows more easily - resistivity decreases </li></ul></ul></ul><ul><ul><ul><li>electrons needed --> “acceptor” or p-type material </li></ul></ul></ul>
  15. 15. P-N Junction <ul><li>Also known as a diode </li></ul><ul><li>One of the basics of semiconductor technology - </li></ul><ul><li>Created by placing n-type and p-type material in close contact </li></ul><ul><li>Diffusion - mobile charges (holes) in p-type combine with mobile charges (electrons) in n-type </li></ul>
  16. 16. P-N Junction <ul><li>Region of charges left behind (dopants fixed in crystal lattice) </li></ul><ul><ul><li>Group III in p-type (one less proton than Si- negative charge) </li></ul></ul><ul><ul><li>Group IV in n-type (one more proton than Si - positive charge) </li></ul></ul><ul><li>Region is totally depleted of mobile charges - “depletion region” </li></ul><ul><ul><li>Electric field forms due to fixed charges in the depletion region </li></ul></ul><ul><ul><li>Depletion region has high resistance due to lack of mobile charges </li></ul></ul>
  17. 17. P-N Junction <ul><li>Reverse bias: </li></ul><ul><ul><li>positive voltage placed on n-type material </li></ul></ul><ul><ul><li>electrons in n-type move closer to positive terminal, holes in p-type move closer to negative terminal </li></ul></ul><ul><ul><li>width of depletion region increases </li></ul></ul><ul><ul><li>allowed current is essentially zero (small “drift” current) </li></ul></ul>
  18. 18. P-N Junction <ul><li>Forward bias: </li></ul><ul><ul><li>positive voltage placed on p-type material </li></ul></ul><ul><ul><li>holes in p-type move away from positive terminal, electrons in n-type move further from negative terminal </li></ul></ul><ul><ul><li>depletion region becomes smaller - resistance of device decreases </li></ul></ul><ul><ul><li>voltage increased until critical voltage is reached, depletion region disappears, current can flow freely </li></ul></ul>
  19. 19. P-N Junction - V-I characteristics <ul><li>Voltage-Current relationship for a p-n junction (diode) </li></ul>
  20. 20. Manufacturing <ul><li>Crystal growth </li></ul><ul><li>Photolithography (masks, patterning) </li></ul><ul><li>Doping </li></ul><ul><li>Packaging/assembly </li></ul><ul><li>Manufacturing environment </li></ul>
  21. 21. Crystal Growth <ul><li>Czochralski method </li></ul><ul><li>Silicon must be crystal to be used in ICs </li></ul><ul><li>Crystal growth - the process of creating crystalline silicon </li></ul><ul><li>Seed crystal (solid piece of crystalline silicon) “brought into contact with the surface of the same material in liquid phase, and then pulled slowly from the melt” [Neaman] </li></ul><ul><li>Liquid cools, solidifies following crystal form </li></ul>
  22. 22. Crystal Growth <ul><li>Ingot cut to uniform diameter, then sliced into wafers </li></ul><ul><li>Wafers machined into uniformed thickness </li></ul><ul><li>Chemically and mechanically smoothed during “lapping” and “polishing” phases </li></ul><ul><li>Completed silicon wafer is known as the substrate material </li></ul>Unmodified ingots
  23. 23. Photolithography <ul><li>Lithography - process of applying circuitry patterns to substrate </li></ul><ul><li>Photolithography - most common lithography technique </li></ul><ul><ul><li>wafer covered with photoresist (light sensitive chemical) </li></ul></ul><ul><ul><li>light shown through a mask onto the photoresist coating </li></ul></ul><ul><ul><li>exposure to light alters properties of photoresist (“hardening”), giving it resistance to certain chemicals </li></ul></ul><ul><ul><li>non-hardened photoresist washed away </li></ul></ul><ul><ul><li>allows for patterns of insulation (SiO 2 ), interconnection (Al), or doping </li></ul></ul><ul><ul><li>many masks/photolithography steps used for complex circuits </li></ul></ul>
  24. 24. Doping <ul><li>“ The technique of adding impurity atoms (dopants) to a semiconductor in order to alter its conductivity” [Neamen] </li></ul><ul><li>Ratio of Si atoms to dopant atoms ranges from </li></ul><ul><li>10 4 :1 to 10 9 :1 </li></ul><ul><ul><li>low level of impurity has large impact on conductivity of substrate </li></ul></ul><ul><li>Impurity diffusion </li></ul><ul><ul><li>substrate placed in high temp. (~1000 C) gaseous atmosphere </li></ul></ul><ul><ul><li>temp. lowered, impurities remain </li></ul></ul><ul><li>Ion implantation </li></ul><ul><ul><li>beam of impurity ions accelerated to high energy, directed at surface of substrate </li></ul></ul>
  25. 25. Testing/Packaging <ul><li>Each circuit on wafer tested, then cut apart </li></ul><ul><li>Circuits are encapsulated in plastic or ceramic molding, retested </li></ul><ul><li>Packages created with leads that allow IC to be attached to printed circuit board </li></ul>
  26. 26. Three Dimensional VLSI <ul><li>The fabrication of a single integrated circuit whose functional parts (transistors, etc) extend in three dimensions </li></ul><ul><li>The vertical orientation of several bare integrated circuits in a single package </li></ul>
  27. 27. Advantages of 3D VLSI <ul><li>Speed - the time required for a signal to travel between the functional circuit blocks in a system (delay) reduced. </li></ul><ul><ul><li>Delay depends on resistance/capacitance of interconnections </li></ul></ul><ul><ul><li>resistance proportional to interconnection length </li></ul></ul>
  28. 28. Advantages of 3D VLSI <ul><li>Noise - “unwanted disturbances on a useful signal” [Al-sarawi] </li></ul><ul><ul><li>reflection noise (varying impedance along interconnect) </li></ul></ul><ul><ul><li>crosstalk noise (interference between interconnects) </li></ul></ul><ul><ul><li>electromagnetic interference (EMI) (caused by current in pins) </li></ul></ul><ul><li>3D chips </li></ul><ul><ul><li>fewer, shorter interconnects </li></ul></ul><ul><ul><li>fewer pins </li></ul></ul>
  29. 29. Advantages of 3D VLSI <ul><li>Power consumption </li></ul><ul><ul><li>power used charging an interconnect capacitance </li></ul></ul><ul><ul><ul><li>P = fCV 2 </li></ul></ul></ul><ul><ul><li>power dissipated through resistive material </li></ul></ul><ul><ul><ul><li>P = V 2 /R </li></ul></ul></ul><ul><ul><li>capacitance/resistance proportional to length </li></ul></ul><ul><ul><li>reduced interconnect lengths will reduce power </li></ul></ul>
  30. 30. Advantages of 3D VLSI <ul><li>Interconnect capacity (connectivity) </li></ul><ul><ul><li>more connections between chips </li></ul></ul><ul><ul><li>increased functionality, ease of design </li></ul></ul>
  31. 31. Advantages of 3D VLSI <ul><li>Printed circuit board size/weight </li></ul><ul><ul><li>planar size of PCB reduced with negligible IC height increase </li></ul></ul><ul><ul><li>weight reduction due to more circuitry per package/smaller PCBs </li></ul></ul><ul><ul><li>estimated 40-50 times reduction in size/weight </li></ul></ul>
  32. 32. 3D VLSI - Challenges and Solutions <ul><li>Challenge: Thermal management </li></ul><ul><ul><li>smaller packages </li></ul></ul><ul><ul><li>increased circuit density </li></ul></ul><ul><ul><li>increased power density </li></ul></ul><ul><li>Solutions: </li></ul><ul><ul><li>circuit layout (design stage) </li></ul></ul><ul><ul><ul><li>high power sections uniformly distributed </li></ul></ul></ul><ul><ul><li>advancement in cooling techniques (heat pipes) </li></ul></ul>
  33. 33. 3D VLSI - Challenges and Solutions <ul><li>Challenge: lack of software to deal with complexity of 3D development </li></ul><ul><li>Solution: same as with increasing 2D complexity - design of improved software </li></ul><ul><li>Challenge: industry’s resistance to change ($) </li></ul><ul><li>Solution: time/research - if proven to be most promising way to continue Moore’s Law growth, investment will be made </li></ul>
  34. 34. Influential Participant - Academia <ul><li>Georgia Tech’s Low Cost Electronics Packaging Research Center </li></ul><ul><ul><li>$40 million facility </li></ul></ul><ul><ul><li>headed by Dr. Rao R. Tummala </li></ul></ul><ul><ul><ul><li>former IBM semiconductor researcher </li></ul></ul></ul><ul><ul><li>goals: </li></ul></ul><ul><ul><ul><li>To carry out research, development and prototype manufacturing </li></ul></ul></ul><ul><ul><ul><li>To transfer this knowledge to industry. </li></ul></ul></ul><ul><ul><ul><li>To train future leaders in electronic package engineering </li></ul></ul></ul>
  35. 35. Influential Participants - Industry <ul><li>Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others... </li></ul><ul><ul><li>high density memories </li></ul></ul><ul><li>AT&T </li></ul><ul><ul><li>high density “multiprocessor” </li></ul></ul><ul><li>Many other applications/participants </li></ul>
  36. 36. Ball Semiconductor, Inc. <ul><li>Unique approach to 3D VLSI </li></ul><ul><ul><li>applying 2D VLSI technologies to surface of 1 mm sphere </li></ul></ul><ul><ul><li>three-dimensional layout tool, called ABLE (Advanced Ball Layout Editor) </li></ul></ul><ul><ul><li>traditional techniques for long rectangle adapted to spherical surface </li></ul></ul><ul><ul><li>over 60% of surface covered </li></ul></ul>
  37. 37. Ball Semiconductor, Inc. Computer Simulation
  38. 38. Ball Semiconductor, Inc Product Developed
  39. 39. Ball Semiconductor, Inc. <ul><li>Complex circuitry achieved with ball stacking </li></ul><ul><li>“ Cubic VLSI by Clustering” </li></ul>
  40. 40. Market <ul><li>Electronics market - $668 billion </li></ul><ul><ul><li>3D VLSI can influence market only with high quality products </li></ul></ul><ul><ul><li>improved quality/low cost will sell </li></ul></ul><ul><li>Little immediate impact expected </li></ul><ul><ul><li>more research and small scale development needed </li></ul></ul><ul><ul><li>expensive change of fabrication process required </li></ul></ul><ul><ul><li>long time-to-market </li></ul></ul><ul><li>Long term impact - today’s will likely be leaders in any 3D IC sales </li></ul><ul><li>3D VLSI will not likely change semiconductor market, only what is sold </li></ul>
  41. 41. Impact - Society <ul><li>Performance improvements </li></ul><ul><ul><li>will occur even without 3D VLSI </li></ul></ul><ul><ul><li>increased influence of computers, cell phones, other common electronic devices </li></ul></ul><ul><ul><li>solution to possible Moore’s Law roadblock </li></ul></ul><ul><li>Size reductions </li></ul><ul><ul><li>drastic compared to 2D VLSI </li></ul></ul><ul><li>Public - ignorant of causes, observant of improvements </li></ul>
  42. 42. Impact <ul><li>Semiconductor Industry </li></ul><ul><ul><li>3D VLSI requires major paradigm shift in industry </li></ul></ul><ul><ul><li>Initial participants - large capital risk to modify fabrication process </li></ul></ul><ul><ul><li>Success of one company will require shift in industry as a whole (competition) </li></ul></ul><ul><li>ECE/CS </li></ul><ul><ul><li>improvements in hardware open software and application possibilities </li></ul></ul>
  43. 43. Three Dimensional VLSI <ul><li>Moore’s Law approaching physical limit </li></ul><ul><li>Increased performance expected by market </li></ul><ul><li>Paradigm shift needed - 3D VLSI </li></ul><ul><ul><li>many advantages over 2D VLSI </li></ul></ul><ul><ul><li>economic limitations of fabrication overhaul will be overcome by market demand </li></ul></ul><ul><li>Three Dimensional VLSI may be the savior of Moore’s Law </li></ul>
  44. 44. End