Computer Architecture Unit 1 AKTU

1. CLASS PRESENTATION
UNIT-1
ANKUR SRIVASTAVA
Assistant Professor,
Dept of CSE,
JETGI, Barabanki

2. CLASS PRESENTATION
Topic-BUS
ANKUR SRIVASTAVA
Assistant Professor,
Dept of CSE,
JETGI, Barabanki

3. LET’S REVISE:-WHAT WE HAVE STUDIED….
1 BUS (definition)
2 Generic BUS structure
3 BUS characteristic
4 Increasing the BUS bandwidth.
5 Advantage & disadvantage of BUS5

4. WHAT WE WILL STUDY IN THIS CLASS….
1 Parallel and Serial Communication
2 Synchronous and Asynchronous BUS
3 Basic Protocol Concepts
4 BUS Arbitration

5. PARALLEL COMMUNICATION. oThat is multiple data control and
possibly power wires with an effective data
transfer unit is 1 bit per wire.
oHigh data throughput with short distances.
oTypically used when the connecting devices
are on the same IC or same board.
oHigher cost, bulky
oBUS must be kept short.
oLong parallel wires result in high
captaincies value which require
more time to charge/discharge
oData misalignment between wires
increases as the length increases.

6. SERIAL COMMUNICATION.
oThat is single data wire, possibly also
control and power wires
oEffective data transfer unit is 1 bit at a time.
oHigh data throughput with long distances.
oCheaper, less bulky
oMore complex interfacing logic and
communication protocol
oSender needs to decompose words into
bits
oReceiver needs to recompose bits into
words.
oControl signal often send on the same wire
as data increasing protocol complexity.

7. SYNCHRONOUS BUS.
oIncludes a clock in the control line.
oA fixed protocol for communication that is
relative to the clock.
oMost of the processor-memory BUSes are
synchronous BUS.
oAdvantages: very little logic and can run very
fast.
oDisadvantages:
oEvery device on the BUS must run
on the same clock rate.
oTo avoid the clock skew they cant
be long if they are fast.

8. ASYNCHORONUS BUS.
oIt is not clocked.
oIt can accommodate a wide
verity of devices.
oIt can be lengthened without
worrying abut clock skew.
oIt requires a handshaking
protocol.

9. BASIC PROTOCAL CONCEPT.
oA BUS transaction include two parts:
oIssuing the command (and address).- request
oTransferring the data.-action
oMaster is the one who starts the BUS transaction by:
oIssuing the command and address.
oSlave is the one who responds to the address by:
oSending data to the master if the master ask for the data
oReceiving data from the master if the master wants to send data.

10. BASIC TRANSACTION PROTOCAL
.

11. A STROBE/HANDSHAKE COMBINATION.

12. WHEN TO USE HANDSHAKE.
oWhen response time
cant be guaranteed in
advance.
oData dependent delay
oComponent variations.

13. BUS ARBITRATION.
oOne of the most important issue in BUS design:
oHow is the BUS reserved by a device that whishes to use it.
oMaster-slave arrangement.
oOnly the bus master can control access to the BUS:
It initiate and control all BUS request.
A slave responds to read and write requests.
oThe simplest system
processor is the only BUS master
All BUS request must be controlled by the processor
Major drawback: the processor is involved in every transaction.

14. ARBITRATION OF MULTIPLE POTENTIAL BUS MASTERS.
oBUS arbitration scheme usually try to balance two factors.
oBUS priority:-the highest priority device must be served first.
oFairness: even the lowest priority device should never be completely
locked out by BUS.
oBUS arbitration scheme can be divided into for classes.
oThe DAISY CHAIN.
oCentralized parallel arbitration.

15. The DAISY CHAIN.

16. CENTRALIZED PARALLEL ARBITRATION.

17. POLLING...

18. POLLING...

19. WHAT NEXT??
SOMETHING AWESOME….
SOME PRACTICAL EXPOSURE OF
TOPICS WE HAVE STUDIED…

20. REGISTER AND BUS TRANSFER

21. TRANSFER FROM BUS TO A DESTINATION REGISTER.

22. ADRESSING MODES

23. LETS BEGAIN WITH AS EXAMPLE..
Suppose we have a two operands instruction
ADD X, Y
X in register
Y in memory
Then, after taking this particular example, we were in fact working out
the series of actions we must take
Next step is to look the various possible ways in which the operands can
be referred to. In other words, what we are talking about is the different
modes in which we can address the data.
That is, modes of addressing the data or referring to the data will usually
be called addressing modes

24. DIFFERENT TYPES OF ADDRESSING MODE?
Immediate Addressing
Direct Addressing
Indirect Addressing
Register Addressing
Register Indirect Addressing
Relative Addressing
Indexed Addressing

25. IMMEDIATE ADDRESSING
Operand is given explicitly in the instruction
Operand = Value
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range
Instruction
opcode operand

26. DIRECT ADDRESSING
Address field contains address of operand
Effective address (EA) = address field (A)
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out effective
address
Limited address space

27. DIRECT ADDRESSING DIAGRAM

28. INDIRECT ADDRESSING
Memory cell pointed to by address field contains
the address of (pointer to) the operand
EA = [A]
Look in A, find address (A) and look there for
operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A to
accumulator

29. INDIRECT ADDRESSING
Large address space
2n where n = word length
May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower

30. INDIRECT ADDRESSING DIAGRAM

31. REGISTER ADDRESSING
Operand is held in register named in
address field
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch

32. REGISTER ADDRESSING
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming or
compiler writing

33. REGISTER ADDRESSING DIAGRAM

34. REGISTER INDIRECT ADDRESSING
C.f. indirect addressing
EA = [R]
Operand is in memory cell pointed to by
contents of register R
Large address space (2n)
One fewer memory access than indirect
addressing

35. REGISTER INDIRECT ADDRESSING DIAGRAM

36. INDEX ADDRESSING
EA = X + [R]
Address field hold two values
X = constant value (offset)
R = register that holds address of memory
locations
or vice versa
(Offset given as constant or in the index register)
Add 20(R1),R2 or Add 1000(R1),R2

37. INDEX ADDRESSING DIAGRAM

38. RELATIVE ADDRESSING
A version of displacement addressing
R = Program counter, PC
EA = X + (PC)
i.e. get operand from X bytes away from
current location pointed to by PC
c.f locality of reference & cache usage

39. AUTO INCREMENT MODE
The effective address of the operand is the
contents of a register specified in the
instruction.
After accessing the operand, the contents of
this register are automatically incremented to
point to the next item in the list
EA=[Ri]; Increment Ri ---- (Ri)+
Eg: Add (R2)+,R0

40. AUTO DECREMENT MODE
The contents of a register specified in the
instruction are first automatically
decremented and are then used as the
effective address of the operand
Decrement Ri; EA= [Ri] ----- -(Ri)

41. THANK YOU!