Addressing

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  • Addressing

    1. 1. William Stallings Computer Organization and Architecture 7 th Edition Chapter 11 Instruction Sets: Addressing Modes and Formats
    2. 2. Addressing Modes <ul><li>Immediate </li></ul><ul><li>Direct </li></ul><ul><li>Indirect </li></ul><ul><li>Register </li></ul><ul><li>Register Indirect </li></ul><ul><li>Displacement (Indexed) </li></ul><ul><li>Stack </li></ul>
    3. 3. Immediate Addressing <ul><li>Operand is part of instruction </li></ul><ul><li>Operand = address field </li></ul><ul><li>e.g. ADD 5 </li></ul><ul><ul><li>Add 5 to contents of accumulator </li></ul></ul><ul><ul><li>5 is operand </li></ul></ul><ul><li>No memory reference to fetch data </li></ul><ul><li>Fast </li></ul><ul><li>Limited range </li></ul>
    4. 4. Immediate Addressing Diagram Operand Opcode Instruction
    5. 5. Direct Addressing <ul><li>Address field contains address of operand </li></ul><ul><li>Effective address (EA) = address field (A) </li></ul><ul><li>e.g. ADD A </li></ul><ul><ul><li>Add contents of cell A to accumulator </li></ul></ul><ul><ul><li>Look in memory at address A for operand </li></ul></ul><ul><li>Single memory reference to access data </li></ul><ul><li>No additional calculations to work out effective address </li></ul><ul><li>Limited address space </li></ul>
    6. 6. Direct Addressing Diagram Address A Opcode Instruction Memory Operand
    7. 7. Indirect Addressing (1) <ul><li>Memory cell pointed to by address field contains the address of (pointer to) the operand </li></ul><ul><li>EA = (A) </li></ul><ul><ul><li>Look in A, find address (A) and look there for operand </li></ul></ul><ul><li>e.g. ADD (A) </li></ul><ul><ul><li>Add contents of cell pointed to by contents of A to accumulator </li></ul></ul>
    8. 8. Indirect Addressing (2) <ul><li>Large address space </li></ul><ul><li>2 n where n = word length </li></ul><ul><li>May be nested, multilevel, cascaded </li></ul><ul><ul><li>e.g. EA = (((A))) </li></ul></ul><ul><ul><ul><li>Draw the diagram yourself </li></ul></ul></ul><ul><li>Multiple memory accesses to find operand </li></ul><ul><li>Hence slower </li></ul>
    9. 9. Indirect Addressing Diagram Address A Opcode Instruction Memory Operand Pointer to operand
    10. 10. Register Addressing (1) <ul><li>Operand is held in register named in address filed </li></ul><ul><li>EA = R </li></ul><ul><li>Limited number of registers </li></ul><ul><li>Very small address field needed </li></ul><ul><ul><li>Shorter instructions </li></ul></ul><ul><ul><li>Faster instruction fetch </li></ul></ul>
    11. 11. Register Addressing (2) <ul><li>No memory access </li></ul><ul><li>Very fast execution </li></ul><ul><li>Very limited address space </li></ul><ul><li>Multiple registers helps performance </li></ul><ul><ul><li>Requires good assembly programming or compiler writing </li></ul></ul><ul><ul><li>N.B. C programming </li></ul></ul><ul><ul><ul><li>register int a; </li></ul></ul></ul><ul><li>c.f. Direct addressing </li></ul>
    12. 12. Register Addressing Diagram Register Address R Opcode Instruction Registers Operand
    13. 13. Register Indirect Addressing <ul><li>C.f. indirect addressing </li></ul><ul><li>EA = (R) </li></ul><ul><li>Operand is in memory cell pointed to by contents of register R </li></ul><ul><li>Large address space (2 n ) </li></ul><ul><li>One fewer memory access than indirect addressing </li></ul>
    14. 14. Register Indirect Addressing Diagram Register Address R Opcode Instruction Memory Operand Pointer to Operand Registers
    15. 15. Displacement Addressing <ul><li>EA = A + (R) </li></ul><ul><li>Address field hold two values </li></ul><ul><ul><li>A = base value </li></ul></ul><ul><ul><li>R = register that holds displacement </li></ul></ul><ul><ul><li>or vice versa </li></ul></ul>
    16. 16. Displacement Addressing Diagram Register R Opcode Instruction Memory Operand Pointer to Operand Registers Address A +
    17. 17. Relative Addressing <ul><li>A version of displacement addressing </li></ul><ul><li>R = Program counter, PC </li></ul><ul><li>EA = A + (PC) </li></ul><ul><li>i.e. get operand from A cells from current location pointed to by PC </li></ul><ul><li>c.f locality of reference & cache usage </li></ul>
    18. 18. Base-Register Addressing <ul><li>A holds displacement </li></ul><ul><li>R holds pointer to base address </li></ul><ul><li>R may be explicit or implicit </li></ul><ul><li>e.g. segment registers in 80x86 </li></ul>
    19. 19. Indexed Addressing <ul><li>A = base </li></ul><ul><li>R = displacement </li></ul><ul><li>EA = A + R </li></ul><ul><li>Good for accessing arrays </li></ul><ul><ul><li>EA = A + R </li></ul></ul><ul><ul><li>R++ </li></ul></ul>
    20. 20. Combinations <ul><li>Postindex </li></ul><ul><li>EA = (A) + (R) </li></ul><ul><li>Preindex </li></ul><ul><li>EA = (A+(R)) </li></ul><ul><li>(Draw the diagrams) </li></ul>
    21. 21. Stack Addressing <ul><li>Operand is (implicitly) on top of stack </li></ul><ul><li>e.g. </li></ul><ul><ul><li>ADD Pop top two items from stack and add </li></ul></ul>
    22. 22. Pentium Addressing Modes <ul><li>Virtual or effective address is offset into segment </li></ul><ul><ul><li>Starting address plus offset gives linear address </li></ul></ul><ul><ul><li>This goes through page translation if paging enabled </li></ul></ul><ul><li>12 addressing modes available </li></ul><ul><ul><li>Immediate </li></ul></ul><ul><ul><li>Register operand </li></ul></ul><ul><ul><li>Displacement </li></ul></ul><ul><ul><li>Base </li></ul></ul><ul><ul><li>Base with displacement </li></ul></ul><ul><ul><li>Scaled index with displacement </li></ul></ul><ul><ul><li>Base with index and displacement </li></ul></ul><ul><ul><li>Base scaled index with displacement </li></ul></ul><ul><ul><li>Relative </li></ul></ul>
    23. 23. Pentium Addressing Mode Calculation
    24. 24. PowerPC Addressing Modes <ul><li>Load/store architecture </li></ul><ul><ul><li>Indirect </li></ul></ul><ul><ul><ul><li>Instruction includes 16 bit displacement to be added to base register (may be GP register) </li></ul></ul></ul><ul><ul><ul><li>Can replace base register content with new address </li></ul></ul></ul><ul><ul><li>Indirect indexed </li></ul></ul><ul><ul><ul><li>Instruction references base register and index register (both may be GP) </li></ul></ul></ul><ul><ul><ul><li>EA is sum of contents </li></ul></ul></ul><ul><li>Branch address </li></ul><ul><ul><li>Absolute </li></ul></ul><ul><ul><li>Relative </li></ul></ul><ul><ul><li>Indirect </li></ul></ul><ul><li>Arithmetic </li></ul><ul><ul><li>Operands in registers or part of instruction </li></ul></ul><ul><ul><li>Floating point is register only </li></ul></ul>
    25. 25. PowerPC Memory Operand Addressing Modes
    26. 26. Instruction Formats <ul><li>Layout of bits in an instruction </li></ul><ul><li>Includes opcode </li></ul><ul><li>Includes (implicit or explicit) operand(s) </li></ul><ul><li>Usually more than one instruction format in an instruction set </li></ul>
    27. 27. Instruction Length <ul><li>Affected by and affects: </li></ul><ul><ul><li>Memory size </li></ul></ul><ul><ul><li>Memory organization </li></ul></ul><ul><ul><li>Bus structure </li></ul></ul><ul><ul><li>CPU complexity </li></ul></ul><ul><ul><li>CPU speed </li></ul></ul><ul><li>Trade off between powerful instruction repertoire and saving space </li></ul>
    28. 28. Allocation of Bits <ul><li>Number of addressing modes </li></ul><ul><li>Number of operands </li></ul><ul><li>Register versus memory </li></ul><ul><li>Number of register sets </li></ul><ul><li>Address range </li></ul><ul><li>Address granularity </li></ul>
    29. 29. PDP-8 Instruction Format
    30. 30. PDP-10 Instruction Format
    31. 31. PDP-11 Instruction Format
    32. 32. VAX Instruction Examples
    33. 33. Pentium Instruction Format
    34. 34. PowerPC Instruction Formats (1)
    35. 35. PowerPC Instruction Formats (2)
    36. 36. Foreground Reading <ul><li>Stallings chapter 11 </li></ul><ul><li>Intel and PowerPC Web sites </li></ul>

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