This document discusses the TMS320VC5416 processor, including its: - Memory map which lists the address ranges for on-chip DARAM memory. - On-chip peripherals such as a DMA controller and three McBSP serial ports. - Features like a 16-bit CPU, single cycle MAC unit, and programmable timer. - Central processing unit components including an arithmetic logic unit and program controller. - Addressing modes like direct, indirect, and register addressing modes.

1. Submitted by:- Submitted To:-
Name:- Shivam Kumar Dr. H P Singh
Class:- B.Tech-EEE HOD, ECE Department
Roll Number:- 1704357
Semester:- 6th

2. Table Of Contents
 Block diagram of TMS320VC5416 Processor
 Memory map
 On chip peripherals
 Memory write and I/O write bus sequence
 General purpose of I/O pins
 Features of TMSC5416
 Central processing unit
 Addressing modes

3. Block Diagram of TMSC5416 Processor

4. Memory Map
The program & data memory map is shown in figure. Address ranges for
on-chip DARAM in data memory are:
 DARAM0: 0080H-1FFFH
 DARAM1: 2000H-3FFFH
 DARAM3: 6000H-7FFFH
 DARAM4: 8000H-9FFFH
 DARAM5: A000H-BFFFH
 DARAM6: C000H-DFFFH
 DARAM7: E000H- FFFFH

5. On chip peripherals
This device has following peripherals:
 Software programmable wait-state generator
 Programmable bank-switching
 A host-port interface (HPI8/16)
 Three multichannel buffered serial ports (McBSPs)
 A hardware timer
 A clock generator with a multiple phase-locked loop (PLL)
 Enhance external parallel interface (XI02)
 A DMA controller

6. Memory write and I/O write bus sequence

7. General purpose of I/O pins
In addition to the standard BIO and XF pins, the device has pins that can be
configured for general purpose I/O
These pins are :
 18 McBSP pins
 BCLKX0/1/2
 BCLKR0/1/2
 BDR0/1/2
 BFSX0/1/2
 BFSR0/1/2
 BDX0/1/2
 8 HPI data pins
 HD0-HD7

8. Features of TMSC5416
 Central Arithmetic Logic Unit
 16 bit CPU
 20-50 ns single cycle instruction
execution time
 Single cycle 16 × 16 bit MAC
unit
 64k × 16 bit external data
memory address space
 64k × 16 bit external program
memory address space
 64k × 16 bit external IO address
space
 2k to 32k × 16 bit single access
on-chip program/data RAM
 32k × 16k bit external global
memory address space
 1k to 9k × 16 bit single access on
chip program/data RAM
 1k × 16 bit dual access on chip
program/data RAM
 Synchronous, TDM and buffered
serial ports
 Programmable timer and PLL
 IEEE standard JTAG poets
 5v/3v operation with low power
dissipation and power down modes
 DMA interface

9. Central processing unit
 Central arithmetic logic unit (CALU)
 Parallel logic unit (PLU)
 Auxiliary register arithmetic unit (ARAU)
 Memory mapped register
 Program controller

10. Addressing modes
The method of specifying the data to be operated by the
instruction is called addressing modes.
 Direct addressing mode
 Memory mapped register addressing mode
 Indirect addressing mode
 Immediate addressing mode
 Register addressing mode
 Circular addressing mode