8086ppt

3,714 views

Published on

Published in: Technology, Business
1 Comment
4 Likes
Statistics
Notes
No Downloads
Views
Total views
3,714
On SlideShare
0
From Embeds
0
Number of Embeds
4
Actions
Shares
0
Downloads
327
Comments
1
Likes
4
Embeds 0
No embeds

No notes for slide

8086ppt

  1. 1. Guided by :- Prof. S.b. Ware
  2. 2.  It is a 16-bit Microprocessor(μp). It’s ALU, internal registers works with 16 bit binary word.  8086 has a 20 bit address bus can access up to 220 = 1 MB memory locations.  8086 has a 16 bit data bus. It can read or write data to a memory/port either 16 bits or 8 bit at a time.  8086 is designed to operate in two modes, Minimum mode and Maximum mode.
  3. 3. Fig: Internal block diagram of 8086 Microprocessor
  4. 4. BUS INTERFACE UNIT
  5. 5. BUS INTERFACE UNIT  BIU provides necessary function including generation of the memory and the input unit.  It transfers data between itself and the surrounding world.  BIU converts logical address into physical address with the help of segment registers.
  6. 6. SEGMENT REGISTERS  BIU contains four 16 bit segment registers, which are as follows:-  Code segment(CS) register  Code segment (64KB)  Data segment (64KB)  Extra segment (64KB)  Stack segment (64KB)
  7. 7. INSTRUCTION POINTER  It is a 16 bit register, which identifies the location of the next word of instruction code that is to be fetched in the current CS.  IP contains an offset instead of the actual address of the next location.  The 20 bit address produced after addition of the offset stored in the IP to the segment base address in the CS is called the physical address of the code byte.
  8. 8.  The last segment of BIU is the FIFO group of registers called as queue.  The arrangement makes it possible for the BIU to fetch the instruction byte while EU is decoding an instruction or executing an instruction which does not require use of buses.  This arrangement is called pipelining which is done to speed up the program execution. THE QUEUE
  9. 9. EXECUTION UNIT
  10. 10. EXECUTION UNIT  The EU of 8086 contains -  Control Circuitry  Instruction decoder  Arithmetic Logic Unit [ALU]  Register Orientation  General Purpose Registers  Flag Registers  Pointers and Index Registers
  11. 11. EXECUTION UNIT – General Purpose Registers AH AL BH BL CH CL DH DL SP BP SI DI 12 8 bits 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index AX BX CX DX Pointer Index 8 bits 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index
  12. 12. EXECUTION UNIT – Flag Register U U U U OF DF IF TF SF ZF U AF U PF U CF 13  A flag is a flip flop which indicates some conditions produced by the execution of an instruction or controls certain operations of the EU . 6 flags indicates some conditions- status flags 3 flags –control Flags Carry Over flow Direction Interrupt Trap Sign Zero Auxiliary Parity U - Unused
  13. 13. Pointer And Index Registers  Used to keep offset addresses. SP: Stack pointer BP: Base Pointer SI: Source Index register DI: Destination Index register 14
  14. 14. Minimum Mode System :-  In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.  In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system.  The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system.  Transceivers are the bidirectional buffers and sometimes they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals.
  15. 15. Minimum Mode 8086 System
  16. 16. Maximum Mode System :-  In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.  In this mode, the processor derives the status signal S2, S1, S0.  Another chip called bus controller derives the control signal using this status information.  In the maximum mode, there may be more than one microprocessor in the system configuration.
  17. 17. Maximum Mode 8086 System
  18. 18. 1. State design factors in design of instruction format. Draw instruction format for Intel processors and explain various fields in it. 2. What are the different types of operand and operations. (08) 3. State and explain any 4 addressing modes with examples for INTEL processors. (08) Dec 2009 4. Draw and explain architecture of Intel processor. 5. State and explain any 4 addressing modes with examples for Intel processors 6. Draw timing diagram for memory read cycle of 8086 and list operations in each T state. 7. Draw timing diagram for memory write cycle of 8086 and list operations in each T state. 8. Write a note on MIN/MAX mode of 8086. Most Probable Questions
  19. 19.  MAYURI SEWATKAR  GAURESH SALGAONKAR  ABHIRUPA SAHA  CHANDAN RAI Presented By :-

×