1. Current Address: Permanent Address:
3 Bayard Road, Apt #27 Yiyi Zhang Shangcheng Road,
Pittsburgh, PA 15213 yiyiz@andrew.cmu.edu Apt #1504, No.1, Lane 108
412-3203789 (Cell) Chinese citizen, F1 visa Shanghai, China
200120 (zip code)
86-13062842096(Cell)
Education: CARNEGIE MELLON UNIVERSITY(CMU), Pittsburgh, PA
Bachelor of Science in Electrical and Computer Engineering Dec 2016
Planning on getting into the Integrated Bachelor and Master Program in CMU and graduate in Dec 2017
Cumulative GPA: 3.91/4.0
Relevant Courses: Microelectronics Circuits
Logic Design and Verification
Signal and Systems
Embedded System Engineering
Introduction to Computer Systems
Electronic Devices and Analog Circuits
Structure and Design of Digital Systems
Introduction to Computer Architecture
Advanced Digital Design Project* Fall 2016
Skills: Programming Languages: C, Assembly(x86, MIPS, ARM), System Verilog, Python, BASH script
Operating Systems: Unix, Mac OS, Windows
Spoken Languages: English (fluent), Chinese(native speaker)
Hardware and Software: Altera/Quartus, Arduino, Cadence, Matlab, Raspberry pi
Working Experiences:
Firmware Engineering Intern at Qualcomm-Atheros San Jose, CA Summer 2015
• develop a debugging tool for a wifi chip that has 200K lines of firmware
• the tool runs on the host side and can be moved easily to other later platforms
18-220 Electronic Devices and Analog Circuits Teaching Assistant Pittsburgh, PA Fall 2015
• responsibilities including TA-ing in lab sessions, doing lab dry run and grading
18-348 Embedded System Engineering Teaching Assistant Pittsburgh, PA Fall 2016
• responsibilities including leading the lab sessions, holding office hour, doing lab dry run and grading
Engineering Intern at Qualcomm Corporate Research and Development San Diego Summer 2016
• Developed an automated software testing tool for the ADC and the RF system used for 5Gtechnology
Projects:
Computer Hardware projects: High performance 64*64 matrix multiplication using FPGA Fall 2015
• implement the matrix multiplication in 160ish CPU clock cycle on FPGA, as opposed to 2000ish clock
cycle in software
Computer Hardware projects: USB HOST Fall 2015
• implement a hardware USB host in system verilog that passes 2106964 test cases including many edge
cases, boundary memory addresses and random test cases.
Computer Hardware projects: Superscalar Processor Spring 2015
• implement 5 stage pipelined superscalor processor with Gshare and Bi-modal branch prediction;
optimized for performance and performance per watts
Firmware projects: Video Game Station based on Freescale HCS12 CPU Spring 2015
• implement a game station “master mind ” and interrupts controlling the overall timing and the hardware
components on board including the LED matrix, LCD screen, PWM and ATD/DTA ports.
Honors: Dean’s list, College of Engineering, CMU: Fall 2013, Spring 2014, Fall 2014, Spring 2015, Fall 2015
Activities: Tau Beta Pi Engineering Honor Society,
Eta Kappa Nu International Electrical and Computer Engineering Honor Society of IEEE