CS304PC:Computer Organization and Architecture Unit- III PDF notes

1. CS307PC
Computer Organization and
Architecture
B.TECH II YEAR – I SEM (R18) (2022-2023)
Prepared
By
Asst.Prof.M.Gokilavani
Department of Computer Science and Engineering (AI/ML)

3. UNIT-III
Data Representation: Data types, Complements, fixed point Representations, Floating point representation.
Computer Arithmetic: Addition and subtraction, multiplication Algorithms, Division Algorithms,
Floating-point Arithmetic operations, Decimal Arithmetic unit, Decimal Arithmetic operations.
Data Representation
• Data types:
• Registers contain either data or control information
• Control information is a bit or group of bits used to specify the sequence of command signals
needed for data manipulation
• Data are numbers and other binary-coded information that are operated on
• Possible data types in registers:
o Numbers used in computations
o Letters of the alphabet used in data processing
o Other discrete symbols used for specific purposes
• All types of data, except binary numbers, are represented in binary-coded form.
• This is because register are made up of Flip-Flops and Flip-Flops are two-state devices that can
store only 1’s and 0’s.
Number System:
A number system of base, or radix, r is a system that uses distinct symbols for r digits. Numbers are
represented by a string of digit symbols.
i. Conversion of Binary to decimal: The string of digits 101101 in the binary number system
represents the quantity
1 x 25
+ 0 x 24
+ 1 x 23
+ 1 x 22
+ 0 x 21
+ 1 x 20
= 45
(101101)2
= (45)10
We will also use the octal (radix 8) and hexadecimal (radix 16) number systems
ii. Conversion of Octal to decimal : (736.4)8
7 x 82
+ 3 x 81
+ 6 x 80
+ 4 x 8-1
= (478.5)10
iii. Conversion of hexadecimal to octal: (F3)16
F x 161
+ 3 x 160
= (243)10
Octal to hexadecimal representation:
• Each octal digit corresponds to three binary digits
• Each hexadecimal digit corresponds to four binary digits
• Rather than specifying numbers in binary form, refer to them in octal or hexadecimal and reduce
the number of digits by 1/3 or ¼, respectively.

4. • Conversion from decimal to radix r system is carried out by separating the number into its integer
and fraction parts and converting each part separately.

5. Decimal representation:
• Numerous different codes can be obtained by arranging four bits in 10 distinct combinations.
• Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where
each digit is represented by a fixed number of bits, usually four or eight.
• Sometimes, special bit patterns are used for a sign or other indications (E.g.: error or
overflow). This particular code is called binary coded decimal and commonly known as
BCD.

6. BCD:
• A binary code is a group of n bits that assume up to 2n
distinct combinations.
• A four bit code is necessary to represent the ten decimal digits – 6 are unused.
• The most popular decimal code is called binary-coded decimal (BCD).
• BCD is different from converting a decimal number to binary.
• For example 99, when converted to binary, is 1100011.
• 99 when represented in BCD is 1001 1001.
ASCII:
• The standard alphanumeric binary code is ASCII
• This uses seven bits to code 128 characters
• Binary codes are required since registers can hold binary information only.

7. • Complements:
 Complements are used in digital computers for simplifying the subtraction operation and
for logical manipulation.
 There are two types of complements for each base r system:
 R’s complement (2’s and 10’s complements)
 (r-1)’s complement (1’s and 9’s complements)
 When the value of the base r is substituted in the name, the two types are referred to as the
2’s and 1’s complement for binary numbers and the 10’s and 9’s complement for decimal
numbers.

8. (r-1)’s complements:
i. 9’s Complement: Given a number N in base r having n digits, the (r – 1)’s complments of N is
defined as (rn
– 1) – N .
 For decimal, the 9’s complement of N is (10n
– 1) – N.
For Example,
• The 9’s complement of 546700 is 999999 – 546700 = 453299
• The 9’s complement of 453299 is 999999 – 453299 = 546700
ii. 1’s complement: For binary, the 1’s complement of N is (2n
– 1) – N.
For Example,
• The 1’s complement of 1011001 is 1111111 – 1011001 = 0100110
r’s Complements:
i. 10’s and 2’s complement: The r’s complement of an n-digit number N in base r is defined as
rn
– N.
• This is the same as adding 1 to the (r – 1)’s complement
For Example,
• The 10’s complement of 2389 is 7610 + 1 = 7611
• The 2’s complement of 101100 is 010011 + 1 = 010100
Subtraction of unsigned numbers:
The subtraction of two n-digits unsigned numbers M-N (N≠0) in base r can be done as follows:
 Add M to the r’s complement of N – this results in
M + (rn
– N) = M – N + rn
 If M > N, the sum will produce an end carry rn
which is discarded.
 If M < N, the sum does not produce an end carry and is equal to
rn
– (N – M), which is the r’s complement of (N – M). To obtain the answer in a
familiar form, take the r’s complement of the sum and place anegative sign in front.
Sample problem 1:

9. Sample problem 2:
• Fixed point representation:
 Positive integers and zero can be represented by unsigned numbers
 Negative numbers must be represented by signed numbers since + and – signs are not
available, only 1’s and 0’s are
 Signed numbers have msb as 0 for positive and 1 for negative – msb is the sign bit
 Two ways to designate binary point position in a register
 Fixed point position
 Floating-point representation
 Fixed point position usually uses one of the two following positions
 A binary point in the extreme left of the register to make it a fraction
 A binary point in the extreme right of the register to make it an integer
 In both cases, a binary point is not actually present
 The floating-point representations uses a second register to designate the position of
the binary point in the first register.

10. Integer representation:
• When an integer is positive, the msb, or sign bit, is 0 and the remaining bits represent the magnitude
• When an integer is negative, the msb, or sign bit, is 1, but the rest of the number can be represented
in one of three ways
• Signed-magnitude representation
• Signed-1’s complement representation
• Signed-2’s complement representation
For Example,
Consider an 8-bit register and the number +14
The only way to represent it is 0000 1110 (8 bits)
Similarly for integer representation,
Consider an 8-bit register and the number –14
Signed magnitude: 1 0001110
Signed 1’s complement: 1 1110001
Signed 2’s complement: 1 1110010
Arithmetic Addition:
Case i: Addition of two signed-magnitude numbers follow the normal rules
• If same signs, add the two magnitudes and use the common sign
• Differing signs, subtract the smaller from the larger and use the sign of the larger
magnitude
• Must compare the signs and magnitudes and then either add or subtract
For Example,
Case ii: Addition of two signed 2’s complement numbers does not require a comparison or
subtraction – only addition and complementation
• Add the two numbers, including their sign bits
• Discard any carry out of the sign bit position
• All negative numbers must be in the 2’s complement form
• If the sum obtained is negative, then it is in 2’s complement form.
For Example,

11. Arithmetic subtraction:
Case i: Subtraction of two signed 2’s complement numbers is as follows
• Take the 2’s complement form of the subtrahend (including sign bit)
• Add it to the minuend (including the sign bit)
• A carry out of the sign bit position is discarded
For Example,
Overflow:
• An overflow occurs when two numbers of n digits each are added and the sum occupies n + 1
digits.
• Overflows are problems since the width of a register is finite.
• Therefore, a flag is set if this occurs and can be checked by the user.
• Detection of an overflow depends on if the numbers are signed or unsigned.
• For unsigned numbers, an overflow is detected from the end carry out of the msb.
• For addition of signed numbers, an overflow cannot occur if one is positive and one is negative
– both have to have the same sign.
• An overflow can be detected if the carry into the sign bit position and the carry out of the sign
bit position are not equal.
For Example,
Decimal fixed point representation:
• The representation of decimal numbers in registers is a function of the binary code used to
represent a decimal digit
• A 4-bit decimal code requires four flip-flops for each decimal digit.
• This takes much more space than the equivalent binary representation and the circuits required
to perform decimal arithmetic are more complex.
• Representation of signed decimal numbers in BCD is similar to the representation of signed
numbers in binary.
• Either signed magnitude or signed complement systems.
• The sign of a number is represented with four bits
• 0000 for +
• 1001 for –
To obtain the 10’s complement of a BCD number, first take the 9’s complement and then add one to
the least significant digits.

12. For Example,
(+375) + (-240) = +135 done in signed 10’s Complement System.
• Floating point representation:
 The floating-point representation of a number has two parts
 The first part represents a signed, fixed-point number – the mantissa
 The second part designates the position of the binary point – the exponent.
 For Example, the decimal number +6132.789 is represented in floating point with a fraction and
an exponent as follows:
Equivalent to +0.6132789 x 10+4
 A floating-point number is always interpreted to represent
 Example: the binary number +1001.11 (with 8-bit fraction and 6-bit exponent)
 Fraction: 01001110
 Exponent: 000100
 Equivalent to +(.1001110)2 x 2+4
 A floating-point number is said to be normalized if the most significant digit of the mantissa is
nonzero.
 The decimal number 350 is normalized, 00350 is not
 The 8-bit number 00011010 is not normalized
 Normalize it by fraction = 11010000 and exponent = -3
 Normalized numbers provide the maximum possible precision for the floating-point number.
Other Binary Codes:
• Digital systems can process data in discrete form only
• Continuous, or analog, information is converted into digital form by means of an analog-to-
digital converter.
• Gray code
• Excess-3
• Excess-3 gray
• Gray Code:
• The reflected binary or Gray code, is sometimes used for the converted digital data.
• The Gray code changes by only one bit as it sequences from one number to the next.
• Gray code counters are sometimes used to provide the timing sequences that control the
operations in a digital system.
• Binary codes for decimal digits require a minimum of four bits.

13. • Other codes besides BCD exist to represent decimal digits.
Excess-3 and Excess-3 gray:
Error Detection Code:
• Transmitted binary information is subject to noise that could change bits 1 to 0 and vice versa.
• An error detection code is a binary code that detects digital errors during transmission.
• The detected errors cannot be corrected, but can prompt the data to be retransmitted.
• The most common error detection code used is the parity bit.

14. • A parity bit is an extra bit included with a binary message to make the total number of 1’s either
odd or even.
• The P(odd) bit is chosen to make the sum of 1’s in all four bits odd
• The even-parity scheme has the disadvantage of having a bit combination of all 0’s .
• Procedure during transmission:
• At the sending end, the message is applied to a parity generator.
• The message, including the parity bit, is transmitted.
• At the receiving end, all the incoming bits are applied to a parity checker.
• Any odd number of errors are detected.
• Parity generators and checkers are constructed with XOR gates (odd function).
• An odd function generates 1 iff an odd number if input variables are 1.

15. Computer Arithmetic
i. Addition and subtraction:
 Arithmetic instructions in digital computer manipulate data to produce results for computational
problems. The four basic arithmetic operations are addition, subtraction, multiplication and
division.
 The solution to any problem that is stated by a finite number of well-defined procedural steps
is called an algorithm.
 Various arithmetic algorithms and show the procedure for implementing them in digital
hardware.
 Types of data are
 Fixed point binary data in signed magnitude representation
 Fixed point binary data in signed 2’s complement representation
 Floating point binary data
 Binary coded decimal (BCD) data
Addition and Subtraction algorithm:
• There are three ways of representing negative fixed-point binary number:
• Signed-magnitude
• Signed 1’s complement
• Signed 2’s complement
• For floating point operation most computers use the signed- magnitude
representation.
Addition and subtraction with signed-magnitude data:
• When the signs of A and B are identical (different), add the two magnitude and attached
the sign of A to the result.
• When the sign of A and B are different (identical, compare the magnitude and subtract
the smaller number from the larger.
• Choose the sign of the result to be same as A if A ˃ B or the complement of the sign of
A if A ˂ B.
• If the magnitude are equal, Subtract B from A and make the sign of the result positive.
Note: The procedure for identical signs in addition algorithm is same as for different sign in
subtraction algorithm.
Hardware Implementation:
• To implement the two-arithmetic operation with hardware, it is necessary that the two numbers
be stored in register.
• Let A and B be two register that holds the magnitude of the numbers, and A1 and B1 be two
flip-flop that holds the corresponding signs.
• The result of the operation is transfer to third register.
• In hardware implementation,
 First, a parallel-adder is needed to perform the microoprations A+B.
 Second a comparator circuit is needed to establish if A ˃ B, A = B, or A ˂ B.

16.  Third two parallel-subtractor circuits are needed to perform the micro-operations
A –B and B –A.
Working of Hardware Implementation:
i. It consists of register A and B and sign flip-flop A1 and B1.
ii. Subtraction is done by adding A and 2’s complement of B.
• The output carry is transferred to flip-flops E, where it can be checked to determine to
relative magnitude of the two numbers.
• The add overflow flip-flop AVF holds the overflow bit when A and B are added.

17. iii. Addition of A and B is done through the parallel adder (consists of full-adder).
• The S (Sum) output of the adder is applied to the input of the A register.
• The complementor (consists of ex-OR gates) provides an output of B or the
complement of B depending on the state of the mode control M.
• When M=0, the output of B is transferred to the adder, the input carry is 0, and the
output of the adder is equal to the sum A+B.
• When M=1, the 1’s complement of B is applied to the adder, the input carry is 1 and
output S=A+B+1.

18. Addition and Subtraction with 2’s complement data:
• The leftmost bit of a binary number represent the sign bit :
• 0 for positive
• 1 for negative
• If the sign bit is 1, the entire number is represented in 2’s complement form.
• The addition of two number is signed complement form consists of adding the numbers with
the sign bits treated the same as the order bits of the number.
• A carry-out of the sign-bit position is discarded. The subtraction consists of first taking 2’s
complement of the subtrahend and then adding it to be minuend.
• When overflow is detected when the output of the gate is equal to 1.

19. ii. Multiplication Algorithms:
Example:
• In multiplication algorithm, successive bits of the multiplier, least significant bit first.
• If the multiplier bit is a 1, the multiplicand is copied down, otherwise zero are copied down.
• The numbers copied down is successive lines are shifted one position to the left from the previous
number. Finally, the numbers are added, and their sum forms the product.
• The sign of the product is determined from the sign of the multiplicand and multiplier.
Multiplication Algorithm:
• The multiplier and multiplicand bits are loaded into two registers Q and M. A third register A
is initially set to zero.
• C is the 1-bit register which holds the carry bit resulting from addition. Now, the control logic
reads the bits of the multiplier one at a time.
• If Q is 1, the multiplicand is added to the register A and is stored back in register A with C bit
used for carry.
• Then all the bits of CAQ are shifted to the right 1 bit so that C bit goes to A , A0 goes to Q
and Q is lost.
• If Q is 0, no addition is performed just do the shift. The process is repeated for each bit of the
original multiplier.
• The resulting 2n bit product is contained in the QA register.

20. Unsigned Binary Multiplication:
There are three types of operation for multiplication.
• It should be determined whether a multiplier bit is 1 or 0 so that it can designate the
partial product.
• If the multiplier bit is 0, the partial product is zero; if the multiplier bit is 1, the
multiplicand is partial product.
• It should shift partial product.
• It should add partial product.
Example:

21. Alternative Method for Unsigned Binary Multiplication:
Algorithm:
• Step 1: Clear the sum (accumulator A). Place the multiplicand in X and multiplier in Y.
• Step 2: Test Y; if it is 1, add content of X to the accumulator A.
• Step 3: Logical Shift the content of X left one position and content of Y right one position.
• Step 4: Check for completion; if not completed, go to step 2

22. Signed Multiplication (Booth Algorithm) – 2’s Complement Multiplication:
Algorithm:
• Multiplier and multiplicand are placed in Q and M register respectively.
• There is also one bit register placed logically to the right of the least significant bit Q of the Q
register and designated as Q.
• The result of multiplication will appear in A and Q resister.
• A and Q are initialized to zero if two bits (Q and Q) are the same (11 or 00) then all the bits of
A, Q and Q registers are shifted to the right 1 bit.
• If the two bits differ then the multiplicand is added to or subtracted from the A register
depending on weather the two bits are 01 or 10.
• Following the addition or subtraction the arithmetic right shift occurs.
• When count reaches to zero, result resides into AQ in the form of signed integer [-2 *a + 2 *a
+ …………… + 2 *a + 2 *a].

23. Array Multiplier:
• Checking the bits of the multiplier one at a time and forming partial products is a sequential
operation that requires a sequence of add and shift micro operations.
• The multiplication of two binary numbers can b done with one micro operation by means of a
combinational circuit that forms the product bits all at once.
• An array multiplier requires a large number of gates, and integrated circuits.

25. iii. Division Algorithms:
• Division of two fixed-point binary numbers in sign-magnitude representation is done with manually
by processing of successive compare, shift and subtract operations.
Rules for Division method:
• First, the bits of the dividend are examined from left to right, until the set of bits examined
represents a number greater than or equal to the divisor: this is referred to as the divisor being
able to divide the number.
• Until this event occurs, 0’s are placed in the quotient from left to right.

26. • When the event occurs, a 1 is placed in the quotient and the divisor is subtracted from the partial
dividend. The result is referred to as a partial remainder.
• The division follows a cyclic pattern. At each cycle, additional bits from the dividend are
appended to the partial remainder until the result is greater than or equal to the divisor.
• Th divisor is subtracted from this number to produce a new partial remainder. The process
continues until all the bits of the dividend are exhausted.
Unsigned Binary Division Algorithm:

27. Algorithm for unsigned binary division:
• Step 1: Initialize A, Q and M registers to Zero, dividend and divisor respectively and counter to
n where n is the number of bits in the dividend.
• Step 2: Shift A, Q left on binary position.
• Step 3: Subtract M from A placing answer back in A. If sign of A is 1, set Q0 to zero and add
M back to A (restore A). If sign of A is 0, set Q0 to 1.
• Step 4: Decrease counter; if counter > 0, repeat process from step 2 else stop the process. The
final remainder will be in A and Quotient will be in Q.
Signed Binary Division Algorithm:
• Step 1: Initialize A, Q and M register to zero, dividend and divisor respectively and count to
number of bits in dividend.
• Step 2: Check sign of A;
• If A<0 (bn-1 is 1)
• Shift A, Q left on binary position.
• Subtract content of M to A and store back in A.
• Step 3: if sign of A is 0, set Q0 to 1 else set Q0 to 0.
• Step 4: Decreased counter. If counter > 0, repeat process from step 2 else go to step 5.
• Step 5: if A≥0 i.e. positive, content of A is remainder else add content of M to A to get the
remainder. The quotient will be in Q.

29. Division Overflow:
• In a computer system, the division operation can lead to a quotient with an overflow because the
registers cannot hold a number that exceeds the standard length. To understand this better, consider
a system with a standard 5-bit register.
• One register is used to hold the divisor and the other to hold the dividend. In case the quotient
consists of 6 bits, 5 bits of the quotient will be stored in a 5-bit register. Therefore, the overflow bit
needs a flip-flop to store the sixth bit.
• The divide overflow condition occurs in case the high-order half bits of the dividend comprises a
number that is greater than or equal to the divisor.
• One other point that needs to be considered in the division is that it is advisable to avoid division by
zero. The overflow condition is generally detected when a flip-flop is set. This flip-flop is known as
DVF.
iv. Floating-point Arithmetic operations:
There are two types of arithmetic operations:-
• Integer Arithmetic
• Real – floating point arithmetic
• Integer Arithmetic: - deals with integer operands.
• i.e. - num without fractional parts
• Real Arithmetic: - use number with fractional parts as operands and is use.
• Real no. = mantissa * 10^exponent
Computer Representation of Floating Point Numbers:
• In the CPU, a 32-bit floating point number is represented using IEEE standard format as
follows:
S | EXPONENT | MANTISSA
Where S is one bit, the EXPONENT is 8 bits, and the MANTISSA is 23 bits.
• The mantissa
• Represents the leading significant bits in the number.
• It is made less than 1 and greater than or equal to 0.1.
• The exponent
• Is used to adjust the position of the binary point (as opposed to a "decimal" point).
• In power of 10 and multiplies with mantissa
Normalization:
• Mantissa and Exponent have their own independent signs.
• While storing no. of the leading digit in the mantissa, mantissa is always made non- zero by
appropriately shifting it and adjusting the value of the exponent.
• The shifting of mantissa to the left till its most significant digit is non- zero is called
normalization.
Example:
• 350->normalized
• 00035-> not normalized.
• Can be normalized by shifting it 3 positions to the left and discarding the leading
zero’s.(10^3)

30. • Zero cannot be normalized because it does not have a nonzero digit. – Denoted by all zeros at
mantissa and exponent.
Arithmetic operations with normalized floating point numbers:
• Addition
• Subtraction
• Multiplication
• Division
Basic Considerations:
• Operations on fp numbers requires complex hardware and takes more time.
• Addition or subtraction requires:
• Alignment of radix point (exponents must be equal).
• Done by shifting mantissa and adjust exponent accordingly.
• Example: 0.5372400*10^2+ 0.1580000*10^-1
• Either shift the 1st no 3 positions to the left or shift the 2nd by 3 position to the right.
• 2nd method is more preferable.
• Normalized addition will cause an overflow and can be corrected by shifting the sum once to
the right and incrementing the exponent.
• Underflow
• Floating point number has a 0 in the MSB of the mantissa.
• Shift the mantissa to the left and decrement the exponent(normalization)
• Multiplication and division does not require alignment.
• Result (multiply mantissa and add the exponent for multiplication).
• Divide the mantissa and subtract the exponent for division.
• The operation performed with exponent are:
• Compare &increment(align mantissa)
• Add &subtract(multiplication and division)
• Decrement ( normalization )
• Exponent representation
• Signed magnitude
• Signed 2’s complement
• Signed 1’s complement
• Biased exponent
• In biased exponent
• Sign bit is not taken as separate entity.
• Is a +ve number that is added to each exponent as the floating point number is formed.
• Internally all exponents are +ve.
• The bias, is subtracted from the field to get the true exponent value.

31. • Bias= (2k-1-1), where k is the number of bits in the binary exponent.
• Advantages
• They contain only positive numbers(easy to compare)
• The smallest possible biased exponent contains all zeros.
v.
vi.

32. Register Configuration:
• The same registers & adders are in the case of fixed point arithmetic are used for processing
mantissa.
• Differs the way in which exponents are handled.
• BR, AC, QR (divided into 2 parts).
• Mantissa is stored in B,A and Q registers
• Exponent in b, a, q registers.
• Mantissa in signed magnitude in A and sign in as and MSB in A1.
• Biased exponent in a.
• A1->1 if the no. Has to be normalized
• Similarly for other registers
• 2 Parallel adders
• 1, Adds two mantissas and sum stores in A, Carry to E.
• 2nd adds the exponents (don’t have distinct sign bit, but taken as +ve).
• Exponent overflow is neglected.
• Exponents are connected to comparator that provides 3 binary outputs to indicate their relative
magnitude.
• The number in the mantissa is taken as a fraction, so binary point resides to the left of the
magnitude part. Numbers are normalized both during initial and after the operation.
Addition and Subtraction:
1. Check for zero’s.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

34. Multiplication:
• Multiply the mantissas and add the exponents.
• No comparison of exponents or alignment of mantissas is necessary.
• Four components:
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas.
4. Normalize the product.

35. Division:
• Floating-point division requires that the exponents be subtracted and the mantissas divided.
• The mantissa division is done as in fixed-point except that the dividend has a single-precision
mantissa that is placed in the AC.
• Check for zeros.
• Initialize registers and evaluate the sign
• Align the dividend (divide overflow check in fix).
• Subtract the exponents.
• Divide the mantissas.

36. v. Decimal Arithmetic unit:
• A CPU with an arithmetic logic unit can perform arithmetic microoprations with binary data.
• A decimal arithmetic unit is a digital function that performs decimal microoprations.
• It can add or subtract decimal numbers, usually by forming the 9’s or 10’s complements of the
subtrahend.
• The unit accepts coded decimal numbers and generates results in the same adopted binary code.

37. BCD Subtraction:
• Subtraction is carried out by adding the ten’s complement negative of the subtrahend to the
minuend.
• Ten’s complement negative of subtrahend is obtained by adding 1 to the nine’s complement
negative of the subtrahend.
• In ten’s complement the number is positive if the left most digit is between 0 and 4 and negative
otherwise.
• The BCD of 4 and 5 are 0100 and 0101 both have 0 in leftmost, 4 indicate positive number and
5 indicate negative number.
• In an excess 3 encoding for each digit the left most bit will indicate the sign
vi. Decimal Arithmetic operations:
• Decimal Arithmetic Unit is a digital function that performs decimal microoprations.
• Can add or subtract decimal numbers, usually by forming the 9's or 10's complement of the
subtrahend.
• The unit accepts coded decimal numbers and generate
• A single-stage decimal arithmetic unit consists of:
– nine binary input variables
– five binary output variables ( since a minimum of four bits is required to represent each
coded decimal digit)
• Each stage must have four inputs for the augends digit, four inputs for the addend digit, and an
input-carry results in the same adopted binary code.
• The outputs include four terminals for the sum digit and one for the output-carry.

38. Addition and Subtraction:
• Addition
– Parallel decimal adder
– Digit-serial. Bit-parallel decimal addition
– All serial decimal addition

39. Multiplication:

40. Division:
• Ae-to accommodate overflow(adding the multiplicand to the partial product)
• Be-to form the 9’s complement of the divisor when subtracted from the partial remainder.