SlideShare a Scribd company logo
1 of 58
BASIC DIGITAL DESIGN
Numbering System
The number system is used for representing the information.
The number system has different bases and the most common of them are
the decimal, binary, octal, and hexadecimal.
The base or radix of the number system is the total number of the digit
used in the number system.
If the number system representing the digit from 0 – 9 then the base of the
system is the 10.
Types of Number Systems
Decimal Number System
The number system is having digit 0, 1, 2, 3, 4, 5, 6, 7, 8, 9;
The base of a system, more properly called the RADIX, is the number of
different values that can be expressed using a single digit.
When writing a number, the digits used give its value, but the number is
scaled by its RADIX POINT.
For example, 456.210 is ten times bigger than 45.6210 although the digits are
the same.
Binary Number System
Binary has only two values 0 and 1. If larger values than 1 are needed, extra
columns are added to the left.
Each column value is now twice the value of the column to its right. For
example the decimal value three is written 11 in binary (1 two + 1 one).
The digital electronic equipment's are works on the binary number system
and hence the decimal number system is converted into binary system.
Octal Number System
Octal has eight values 0 to 7. If larger values than 7 are needed, extra
columns are added to the left.
The octal system has the base of eight as it uses eight digits 0, 1, 2, 3, 4, 5,
6, 7.
The next digit in the octal number is represented by 10, 11, 12, which are
equivalent to decimal digits 8, 9, 10 respectively.
The main advantage of using octal number system is that it can be
converted directly to binary in a very easy manner.
Hexadecimal Number System
• The hexadecimal number system has a base of 16, and hence it consists of
the following sixteen number of digits.
• 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F.
• This Hexadecimal system is used in computer registers to store the
addresses of the data. If we have to give a large number of binary strings.
• For suppose 1011110110001011111010110001101, it is very much difficult
and create a lot of confusion. So computer uses Hexadecimal numbers in
representation of such strings.
Number System Conversions
Any radix to Decimal number system D= 𝑖=−𝑛
𝑝−1
𝑑𝑖. 𝑟 𝑖
.
Where p is No. of digits to the left of the radix point.
n is No. of digits to the right of the radix point.
d is value of the number.
r is radix of the number system.
The number based conversions are essential in digital electronics. Why
because, in all digital system, we have the input in decimal format.
While computation system need binary conversion and result will be
Hexadecimal format by inverse conversion.
Hexadecimal to binary conversion
To convert a hexadecimal number to a binary number, convert each
hexadecimal digit to its four digit equivalent.
For example, consider the hexadecimal number 9AF which is converted into
a binary digit. The conversions are explained below.
Binary to Hexadecimal conversion
To convert the given binary number into its equivalent hexadecimal number
rewrite the binary number of the sets of four digits.
Then place the hexadecimal digit in front of each four digit set of a binary
number as explained by the following number.
Hexadecimal to Decimal conversion
The base of the hexadecimal number system is 16, therefore the weights
corresponding to various positions of the digits will be as shown below.
For instance, consider the conversion of hexadecimal number E8F6.27 into
its equivalent binary number.
 Therefore E8f6.27 written in decimal as 59638.1523437.
Decimal to Hexadecimal conversion
The conversion of the given decimal number into hexadecimal number
requires the application of hex-dabble method.
Consider the conversion of the decimal number 3749 into its hexadecimal
equivalent number.
The third reminder 13 is equivalent to D in a hexadecimal number system.
Thus the equivalent hexadecimal number D97.
Decimal to Binary
(10.25)10
(10.25)10 = (1010.01)2
Number System Conversions
Binary to Decimal:
(1010.01)2
1×23 + 0x22 + 1×21+ 0x20 + 0x2 -1 + 1×2 -2 = 8+0+2+0+0+0.25 =
10.25
(1010.01)2 = (10.25)10
 Decimal to Octal
(10.25)10
(10)10 = (12)8 ; And Fractional part:0.25 x 8 = 2.00
(10.25)10 = (12.2)8
Number System Conversions
 Octal to Decimal
(12.2)8
1 x 81 + 2 x 80 +2 x 8-1 = 8+2+0.25 = 10.25
(12.2)8 = (10.25)10
Hexadecimal to octal Number
First the individual digits are converted into its binary bits. After that
the subsequent bits are grouped into 3 bits.
(ABCD)16
A (1010) , B (1011), C (1100), D(1101)
001 010 101 111 001 101 (pairing 3 binary bits)
So, (ABCD)16 =(125715)8
Signed Magnitude Representation
MSB of a bit string is used as the sign bit and the lower bits contain the
magnitude.
Ex: (1111)2= (15)10 unsigned number representation.
(01111)2= +(15)10
(11111)2= −(15)10 signed number representation.
Range of the n bit signed magnitude integer is given as
- (2 𝑛−1
-1) to + (2 𝑛−1
-1) to
Complement of Numbers
There are two types of complements for each base-r system.
1. r's complement , 2. (r -1)'s complement.
Ex: The 9’s complement of 546700 is 999999-546700=453299
For binary numbers, r = 2 and r –1 = 1, so the 1's complement of N is
(2^n -1) –N.
Ex: The 1’s complement of 1011000is 0100111.
Complement of Numbers
Radix Complement
The r's complement of an n-digit number N in base r is defined as 𝑟 𝑛–N for
N ≠ 0 and as 0 for N = 0.
Comparing with the (r -1) 's complement, we note that the r’s complement
is obtained by adding 1 to the (r-1) 's complement, since
𝑟 𝑛–N = [(𝑟 𝑛-1)–N] + 1.
Ex: The 10's complement of 012398 is 987602
Ex: The 2's complement of 1101100 is 0010100
Compliment of Numbers
The subtraction of two n-digit unsigned numbers M –N in base r can be
done as follows:
Compliment of Numbers
Using 10's complement, subtract 72532 –3250.
Using 10's complement, subtract 3250 –72532
Here no end carry, Therefore, the answer is –(10's complement of 30718) is
- 69282.
CODES
In the coding, when numbers or letters are represented by a specific group
of symbols, that group of symbols is called as code or Binary code.
If the code has positional weights, then it is said to be weighted code.
Otherwise, it is an unweighted code.
Codes are required to conveniently input data into digital system and
interpret results.
CODES
Binary codes classification
CODES
Weighted codes: In weighted codes, each digit is assigned a specific weight
according to its position. For example, in 8421BCD code, 1001 the weights
of 1, 0, 0, 1 (from left to right) are 8, 4, 2 and 1 respectively.
The codes 8421BCD, 2421BCD, 5211BCD are all weighted codes.
Non-weighted codes: The non-weighted codes are not positionally
weighted. In other words, each digit position within the number is not
assigned a fixed value ( or weight ).
Excess-3 and gray code are non-weighted codes.
CODES
Reflective codes: A code is reflective when the code is self complementing.
In other words, when the code for 9 is the complement the code for 0, 8 for
1, 7 for 2, 6 for 3 and 5 for 4.
2421BCD, 5421BCD and Excess-3 code are reflective codes.
 Sequential codes: In sequential codes, each succeeding code is one binary
number greater than its preceding code. This property helps in
manipulation of data.
8421 BCD and Excess-3 are sequential codes.
CODES
Alphanumeric codes: Codes used to represent numbers, alphabetic
characters, symbols and various instructions necessary for conveying
intelligible information.
ASCII, EBCDIC, UNICODE are the most-commonly used alphanumeric codes.
 Error detecting and correcting codes: Codes which allow error detection
and correction are called error detecting and correcting codes. Hamming
code is the mostly commonly used error detecting and correcting code.
Binary Coded Decimal(BCD) Code
In this code each decimal digit is represented by a 4-bit binary number.
BCD is a way to express each of the decimal digits with a binary code.
In the BCD, with four bits we can represent sixteen numbers (0000 to 1111).
But in BCD code only first ten of these are used (0000 to 1001).
The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD.
Ex: (874)10= (1000 0111 0100) 𝑏𝑐𝑑
Excess-3 Code
• It is non-weighted code used to express decimal numbers. The Excess-3
code words are derived from the 8421 BCD code.
Gray Code
It is the non-weighted code and it is not arithmetic codes. That means there
are no specific weights assigned to the bit position.
It has a very special feature that, only one bit will change each time.
the gray code is called as a unit distance code.
The gray code is a cyclic code.
Gray code cannot be used for arithmetic operation.
For Low power applications Gray code will be useful.
Codes Conversion
There are many methods or techniques which can be used to convert code
from one format to another. We'll demonstrate here the following.
1.Binary to BCD Conversion
2.BCD to Binary Conversion
3.BCD to Excess-3
4.Excess-3 to BCD
Binary to BCD conversion
Step 1 -- Convert the binary number to decimal.
Step 2 -- Convert decimal number to BCD.
• Ex: binary number is (11101)2
• Binary Number −> (11101)2 = Decimal Number −> (29)10
(29)10 =(00101001)BCD
BCD to Binary conversion
Step 1 -- Convert the BCD number to decimal.
Step 2 -- Convert decimal to binary.
Ex: convert (00101001)BCD to Binary.
(00101001)BCD => 00102 10012 => 210 910 =>
Decimal Number −> (29)10
Decimal Number −> 2910 = Binary Number −> (11101)2
BCD to Excess-3 conversion
Step 1 -- Convert BCD to decimal.
Step 2 -- Add (3)10 to this decimal number.
Step 3 -- Convert into binary to get excess-3 code.
Ex: convert (1001)BCD to Excess-3.
Step 1 − Convert to decimal
(1001)BCD = 910
Step 2 − Add 3 to decimal
(9)10 + (3)10 = (12)10
Step 3 − Convert to Excess-3
(12)10 = (1100)2
Excess-3 to BCD conversion
• Step 1 -- Subtract (0011)2 from each 4 bit of excess-3 digit to obtain the
corresponding BCD code.
Ex: convert (10011010)XS-3 to BCD.
Ex-3 -> 1001 1010
subtract (0011)2 -> 0011 0011
result BCD -> 0110 0111
(10011010)XS-3 = (01100111)BCD
Binary to Gray Conversion
The first bit(MSB) of the gray code is the same as the first bit of the binary
number
The second bit of the gray code equals the exclusive OR of the first and
second bits of the binary number from MSB
The third bit of the gray code equals the exclusive OR of the second and
third bits of the binary number and so on.
 Ex: (01001)2= (01101) gray
Gray to Binary Conversion
The M.S.B of the binary number will be equal to the M.S.B of the given gray
code.
Now if the second gray bit is 0 the second binary bit will be same as the
previous or the first bit. If the gray bit is 1 the second binary bit will alter. If
it was 1 it will be 0 and if it was 0 it will be 1.
This step is continued for all the bits to do Gray code to binary conversion.
 Ex: (01101) gray = (01001)2
UNIVERSEL GATES
 A Gate which can be use to create any Logic Gate is called Universal Gate.
 NAND and NOR Gates are called Universal Gates because all the other Gates can be created by
using these Gates.
 NAND and NOR Gates can implement any logical Boolean expression.
 In practice, this is advantageous since NAND and NOR gates are economical and easier to
fabricate and are the basic gates used in all IC digital logic families.
NAND Gate
NAND function is compliment of the AND function.
NAND consist of an AND graphic symbol followed by a small circle.
 Its name is an abbreviation of NOT AND .
NAND output logical expression is given as z = 𝑥. 𝑦
x y z
0 0 1
0 1 1
1 0 1
1 1 0
x
y
z
Truth table for NAND Gate
Fig:Logic symbol for NAND
Gate
Inverter implementation by NAND Gate
All NAND input pins connect to the input signal A gives an output 𝐴.
One NAND input pin is connected to the input signal A while all other input
pins are connected to logic 1. The output will be 𝐴.
A 𝐴 𝐴
A
1
A ~A
0 1
1 0
Truth table for NOT
Gate
Fig: NOT Gate implementation by NAND Gate
AND Gate implementation by NAND Gate
The AND is replaced by a NAND gate with its output complemented by a
NAND gate inverter .
A 𝑨. 𝑩
Truth table for AND
Gate
Fig:AND Gate implementation by NAND Gate
A
B
𝑨. 𝑩
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate implementation by NAND Gate
The OR gate is replaced by a NAND gate with all its inputs complemented by
NAND gate inverters .
Truth table for OR
Gate
Fig:OR Gate implementation by NAND Gate
A
B
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
𝑨
𝑩
𝑨. 𝑩
NOR Gate implementation by NAND Gate
A NOR gate is simply an OR gate with an inverted output:
Truth table for NOR Gate
Fig:NOR Gate implementation by NAND Gate
A B
Q=𝑥 + 𝑦
0 0 1
0 1 0
1 0 0
1 1 0
XOR Gate implementation by NAND Gate
The output of an XOR gate is true only when one of its inputs is true.
 If both of an XOR gate's inputs are false, or if both of its inputs are true,
then the output of the XOR gate is false.
Logical symbol is given as
Truth table for XOR
Gate
Fig:XOR Gate implementation by NAND Gate
A B Q=
0 0 0
0 1 1
1 0 1
1 1 0
A ⊕ B
XNOR Gate implementation by NAND Gate
The output of an XNOR gate is true when all of its inputs are true or when
all of its inputs are false.
 If some of its inputs are true and others are false, then the output of the
XNOR gate is false.
 Logical symbol is given like
Truth table for XNOR
Gate
Fig: XNOR Gate implementation by
NAND Gate
A B Q=
0 0 1
0 1 0
1 0 0
1 1 1
A
B
𝐴 ⊕ 𝐵
𝐴 ⊕ 𝐵
NOR Gate
NOR function is compliment of the AND function.
NOR consist of an OR graphic symbol followed by a small circle.
 Its name is an abbreviation of NOT OR .
NOR output logical expression is given as z = 𝑥 + 𝑦
x y z
0 0 1
0 1 0
1 0 0
1 1 0
x
y
z
Truth table for NOR Gate
Fig: Logic symbol for NOR
Gate
Inverter implementation by NOR Gate
All NOR input pins connect to the input signal A gives an output 𝐴.
One NOR input pin is connected to the input signal A while all other input
pins are connected to logic 0. The output will be 𝐴.
Fig: NOT Gate implementation by NOR Gate
AND Gate implementation by NOR Gate
An AND gate gives a 1 output when both inputs are 1;
a NOR gate gives a 1 output only when both inputs are 0.
 Therefore, an AND gate is made by inverting the inputs to a NOR gate
Truth table for AND
Gate
Fig: AND Gate implementation by NOR Gate
A B
Q=A.B
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate implementation by NOR Gate
The OR gate is simply a NOR gate followed by a NOT gate.
Truth table for OR
Gate
Fig: OR Gate implementation by NOR Gate
A B Q=
A+B
0 0 0
0 1 1
1 0 1
1 1 1
NAND Gate implementation by NOR Gate
A NAND gate is made using an AND gate in series with a NOT gate
A B
Q=𝐴. 𝐵
0 0 1
0 1 1
1 0 1
1 1 0Truth table for NAND Gate
Fig: NAND Gate implementation by NOR Gate
XOR Gate implementation by NOR Gate
An XOR gate is made by connecting the output of 3 NOR gates.
 This expresses the logical formula (A AND B) NOR (A NOR B).
This construction require a propagation delay three times that of a single
NOR gate and uses five gates.
Logical symbol is given as
Truth table for XOR
Gate
Fig:XOR Gate implementation by NOR Gate
A B Q=
0 0 0
0 1 1
1 0 1
1 1 0
A ⊕ B
XNOR Gate implementation by NOR Gate
An XNOR gate can be constructed from four NOR gates implementing the
expression (A NOR N) NOR (B NOR N) where N = A NOR B.
This construction entails a propagation delay three times that of a single
NOR gate and uses four gates.
Logical symbol is given as
Truth table for XNOR
Gate
Fig:XNOR Gate implementation by NOR Gate
A B Q=
0 0 1
0 1 0
1 0 0
1 1 1
𝐴 ⊕ 𝐵
Canonical and Standard forms
In Boolean algebra, Boolean function can be expressed as Canonical
Disjunctive Normal Form known as minterm .
And some are expressed as Canonical Conjunctive Normal Form known as
maxterm .
minterm for each combination of the variables that produces a 1 in the
function and then taking the OR of all those terms.
maxterm for each combination of the variables that produces a 0 in the
function and then taking the AND of all those terms
Boolean functions expressed as a sum of minterms(SOP) or product of
maxterms(POS) are said to be in canonical form.
Truth table Notation for Minterms and Maxterm
• Example: Assume 3 Literals x,y,z .
Sum of minterm
With ‘n’ variable, maximum possible minterms are 2^n.
Ex: Express the Boolean function F = A + B’C as a sum of minterms.
• First term A = A(B + B’) = AB + AB’
A = AB(C + C’) + AB'(C + C’) = ABC + ABC’+ AB’C + AB’C’
• second term B’C = B’C(A + A’) = AB’C + A’B’C
F = A + B’C = ABC + ABC’ + AB’C + AB’C’ + A’B’
here AB’C appears twice, from Boolean theorems
F = A’B’C + AB’C + AB’C + ABC’ + ABC= m1 + m4 + m5 + m6 + m7
SOP is represented as ∑1, 4, 5, 6, 7) .
Product of maxterm
Ex: Express the Boolean function F = xy + x’z as a product of maxterms
sol: F = xy + x’z
= (xy + x’)(xy + z)
= (x + x’)(y + x’)(x + z)(y + z)
= (x’ + y)(x + z)(y + z)
x’ + y = x’ + y + zz’
= (x’+ y + z)(x’ + y + z’)
x + z = x + z + yy’
= (x + y + z)(x + y’ + z)
y + z = y + z + xx’
= (x + y + z)(x’ + y + z)
F = (x + y + z)(x + y’ + z)(x’ + y + z)(x’ + y + z’)
= M0*M2*M4*M5
POS is represented as ∏(0, 2, 4, 5)
With ‘n’ variable, maximum possible maxterms are 2^n.
Conversion between canonical Forms
Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the
original form with those that do not.
Example:
f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m2 + m4 + m6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
Standard Forms
Standard forms are like canonical forms, except that not all variables need
appear in the individual product (SOP) or sum (POS) terms.
Example:
f1(a,b,c) = a’b’c + bc’ + ac’
is a standard sum-of-products form
f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
is a standard product-of-sums form.
Conversion of SOP from standard to canonical form
Expand non-canonical terms by inserting equivalent of 1 in each missing
variable x:
(x + x’) = 1
Remove duplicate minterms
f1(a,b,c) = a’b’c + bc’ + ac’
= a’b’c + (a+a’)bc’ + a(b+b’)c’
= a’b’c + abc’ + a’bc’ + abc’ + ab’c’
= a’b’c + abc’ + a’bc + ab’c’
Conversion of POS from standard to canonical form
Expand noncanonical terms by adding 0 in terms of missing variables (e.g.,
xx’ = 0) and using the distributive law
Remove duplicate maxterms
f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
= (a+b+c)•(aa’+b’+c’)•(a’+bb’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•
(a’+b+c’)•(a’+b’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)

More Related Content

What's hot

Forward error correction
Forward error correctionForward error correction
Forward error correctionPrankit Mishra
 
Universal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliUniversal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliDipayan Sarkar
 
Encoder and decoder
Encoder and decoderEncoder and decoder
Encoder and decoderAbid Ali
 
Digital electronics- BCD & Decoder
Digital electronics- BCD & DecoderDigital electronics- BCD & Decoder
Digital electronics- BCD & DecoderPritam Shil
 
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
 
The BCD to excess-3 converter
The BCD to excess-3 converterThe BCD to excess-3 converter
The BCD to excess-3 converterMahady Hasan
 
3.codes( binary code ,excess 3, gray code )
3.codes( binary code ,excess 3, gray code )3.codes( binary code ,excess 3, gray code )
3.codes( binary code ,excess 3, gray code )MdFazleRabbi18
 
Digital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 unitsDigital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 unitsLekashri Subramanian
 
Memory elements
Memory elementsMemory elements
Memory elementschandkec
 
Design half ,full Adder and Subtractor
Design half ,full Adder and SubtractorDesign half ,full Adder and Subtractor
Design half ,full Adder and SubtractorJaimin@prt.ltd.
 
Digital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebraDigital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebraelfeds916
 
KARNAUGH MAP(K-MAP)
KARNAUGH MAP(K-MAP)KARNAUGH MAP(K-MAP)
KARNAUGH MAP(K-MAP)mihir jain
 
VLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVishal kakade
 
PROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAs
PROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAsPROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAs
PROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAsDianaD43
 

What's hot (20)

Forward error correction
Forward error correctionForward error correction
Forward error correction
 
Universal Gates - Aneesa N Ali
Universal Gates - Aneesa N AliUniversal Gates - Aneesa N Ali
Universal Gates - Aneesa N Ali
 
Encoder and decoder
Encoder and decoderEncoder and decoder
Encoder and decoder
 
Digital electronics- BCD & Decoder
Digital electronics- BCD & DecoderDigital electronics- BCD & Decoder
Digital electronics- BCD & Decoder
 
Number system
Number systemNumber system
Number system
 
LDPC Codes
LDPC CodesLDPC Codes
LDPC Codes
 
Division algorithm
Division algorithmDivision algorithm
Division algorithm
 
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
 
Number system
Number systemNumber system
Number system
 
The BCD to excess-3 converter
The BCD to excess-3 converterThe BCD to excess-3 converter
The BCD to excess-3 converter
 
3.codes( binary code ,excess 3, gray code )
3.codes( binary code ,excess 3, gray code )3.codes( binary code ,excess 3, gray code )
3.codes( binary code ,excess 3, gray code )
 
Digital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 unitsDigital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 units
 
Memory elements
Memory elementsMemory elements
Memory elements
 
Number system
Number system Number system
Number system
 
Design half ,full Adder and Subtractor
Design half ,full Adder and SubtractorDesign half ,full Adder and Subtractor
Design half ,full Adder and Subtractor
 
Digital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebraDigital systems logicgates-booleanalgebra
Digital systems logicgates-booleanalgebra
 
Encoders and decoders
Encoders and decodersEncoders and decoders
Encoders and decoders
 
KARNAUGH MAP(K-MAP)
KARNAUGH MAP(K-MAP)KARNAUGH MAP(K-MAP)
KARNAUGH MAP(K-MAP)
 
VLSI subsystem design processes and illustration
VLSI subsystem design processes and illustrationVLSI subsystem design processes and illustration
VLSI subsystem design processes and illustration
 
PROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAs
PROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAsPROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAs
PROGRAMMABLE LOGIC DEVICES-PAL, PROM,PLAs
 

Similar to DIGITAL DESIGN

Similar to DIGITAL DESIGN (20)

Digital Electronics- Number systems & codes
Digital Electronics- Number systems & codes Digital Electronics- Number systems & codes
Digital Electronics- Number systems & codes
 
1.Digital Electronics overview & Number Systems.pptx
1.Digital Electronics overview & Number Systems.pptx1.Digital Electronics overview & Number Systems.pptx
1.Digital Electronics overview & Number Systems.pptx
 
Number Systems
Number SystemsNumber Systems
Number Systems
 
FYBSC IT Digital Electronics Unit I Chapter I Number System and Binary Arithm...
FYBSC IT Digital Electronics Unit I Chapter I Number System and Binary Arithm...FYBSC IT Digital Electronics Unit I Chapter I Number System and Binary Arithm...
FYBSC IT Digital Electronics Unit I Chapter I Number System and Binary Arithm...
 
NUMBER SYSTEM.pptx
NUMBER SYSTEM.pptxNUMBER SYSTEM.pptx
NUMBER SYSTEM.pptx
 
chap1.pdf
chap1.pdfchap1.pdf
chap1.pdf
 
chap1.pdf
chap1.pdfchap1.pdf
chap1.pdf
 
chap1.pdf
chap1.pdfchap1.pdf
chap1.pdf
 
Data representation
Data representationData representation
Data representation
 
Csc 2313 (lecture 3)
Csc 2313 (lecture 3)Csc 2313 (lecture 3)
Csc 2313 (lecture 3)
 
Csc 2313 (lecture 3)
Csc 2313 (lecture 3)Csc 2313 (lecture 3)
Csc 2313 (lecture 3)
 
Digital electronics number system notes
Digital electronics number system notesDigital electronics number system notes
Digital electronics number system notes
 
Number system
Number systemNumber system
Number system
 
Numsys
NumsysNumsys
Numsys
 
Data repersentation.
Data repersentation.Data repersentation.
Data repersentation.
 
Cse 112 number system-[id_142-15-3472]
Cse 112 number system-[id_142-15-3472]Cse 112 number system-[id_142-15-3472]
Cse 112 number system-[id_142-15-3472]
 
DLD_PPT_0.pptx
DLD_PPT_0.pptxDLD_PPT_0.pptx
DLD_PPT_0.pptx
 
Data Representation
Data RepresentationData Representation
Data Representation
 
IARE_DLD_PPT_0.pdf
IARE_DLD_PPT_0.pdfIARE_DLD_PPT_0.pdf
IARE_DLD_PPT_0.pdf
 
Number system
Number systemNumber system
Number system
 

More from HARINATH REDDY

Sv data types and sv interface usage in uvm
Sv data types and sv interface usage in uvmSv data types and sv interface usage in uvm
Sv data types and sv interface usage in uvmHARINATH REDDY
 
High Bandwidth Memory(HBM)
High Bandwidth Memory(HBM)High Bandwidth Memory(HBM)
High Bandwidth Memory(HBM)HARINATH REDDY
 
UVM Driver sequencer handshaking
UVM Driver sequencer handshakingUVM Driver sequencer handshaking
UVM Driver sequencer handshakingHARINATH REDDY
 
System verilog assertions
System verilog assertionsSystem verilog assertions
System verilog assertionsHARINATH REDDY
 

More from HARINATH REDDY (7)

Ambha axi
Ambha axiAmbha axi
Ambha axi
 
Sv data types and sv interface usage in uvm
Sv data types and sv interface usage in uvmSv data types and sv interface usage in uvm
Sv data types and sv interface usage in uvm
 
High Bandwidth Memory(HBM)
High Bandwidth Memory(HBM)High Bandwidth Memory(HBM)
High Bandwidth Memory(HBM)
 
UVM Driver sequencer handshaking
UVM Driver sequencer handshakingUVM Driver sequencer handshaking
UVM Driver sequencer handshaking
 
Flow measurement
Flow measurementFlow measurement
Flow measurement
 
System verilog assertions
System verilog assertionsSystem verilog assertions
System verilog assertions
 
GFSK DEMODULATOR
GFSK DEMODULATORGFSK DEMODULATOR
GFSK DEMODULATOR
 

Recently uploaded

Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024hassan khalil
 
main PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfidmain PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfidNikhilNagaraju
 
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)dollysharma2066
 
Electronically Controlled suspensions system .pdf
Electronically Controlled suspensions system .pdfElectronically Controlled suspensions system .pdf
Electronically Controlled suspensions system .pdfme23b1001
 
Risk Assessment For Installation of Drainage Pipes.pdf
Risk Assessment For Installation of Drainage Pipes.pdfRisk Assessment For Installation of Drainage Pipes.pdf
Risk Assessment For Installation of Drainage Pipes.pdfROCENODodongVILLACER
 
Application of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptxApplication of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptx959SahilShah
 
Biology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptxBiology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptxDeepakSakkari2
 
Effects of rheological properties on mixing
Effects of rheological properties on mixingEffects of rheological properties on mixing
Effects of rheological properties on mixingviprabot1
 
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...srsj9000
 
Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.eptoze12
 
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...VICTOR MAESTRE RAMIREZ
 
An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...Chandu841456
 
Call Girls Narol 7397865700 Independent Call Girls
Call Girls Narol 7397865700 Independent Call GirlsCall Girls Narol 7397865700 Independent Call Girls
Call Girls Narol 7397865700 Independent Call Girlsssuser7cb4ff
 
GDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentationGDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentationGDSCAESB
 
Arduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.pptArduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.pptSAURABHKUMAR892774
 
Heart Disease Prediction using machine learning.pptx
Heart Disease Prediction using machine learning.pptxHeart Disease Prediction using machine learning.pptx
Heart Disease Prediction using machine learning.pptxPoojaBan
 
Past, Present and Future of Generative AI
Past, Present and Future of Generative AIPast, Present and Future of Generative AI
Past, Present and Future of Generative AIabhishek36461
 
Internship report on mechanical engineering
Internship report on mechanical engineeringInternship report on mechanical engineering
Internship report on mechanical engineeringmalavadedarshan25
 
Introduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptxIntroduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptxk795866
 

Recently uploaded (20)

Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024
 
main PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfidmain PPT.pptx of girls hostel security using rfid
main PPT.pptx of girls hostel security using rfid
 
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
Call Us ≽ 8377877756 ≼ Call Girls In Shastri Nagar (Delhi)
 
Electronically Controlled suspensions system .pdf
Electronically Controlled suspensions system .pdfElectronically Controlled suspensions system .pdf
Electronically Controlled suspensions system .pdf
 
Risk Assessment For Installation of Drainage Pipes.pdf
Risk Assessment For Installation of Drainage Pipes.pdfRisk Assessment For Installation of Drainage Pipes.pdf
Risk Assessment For Installation of Drainage Pipes.pdf
 
Application of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptxApplication of Residue Theorem to evaluate real integrations.pptx
Application of Residue Theorem to evaluate real integrations.pptx
 
Biology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptxBiology for Computer Engineers Course Handout.pptx
Biology for Computer Engineers Course Handout.pptx
 
Effects of rheological properties on mixing
Effects of rheological properties on mixingEffects of rheological properties on mixing
Effects of rheological properties on mixing
 
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
Gfe Mayur Vihar Call Girls Service WhatsApp -> 9999965857 Available 24x7 ^ De...
 
Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.
 
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
 
An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...An experimental study in using natural admixture as an alternative for chemic...
An experimental study in using natural admixture as an alternative for chemic...
 
Call Girls Narol 7397865700 Independent Call Girls
Call Girls Narol 7397865700 Independent Call GirlsCall Girls Narol 7397865700 Independent Call Girls
Call Girls Narol 7397865700 Independent Call Girls
 
POWER SYSTEMS-1 Complete notes examples
POWER SYSTEMS-1 Complete notes  examplesPOWER SYSTEMS-1 Complete notes  examples
POWER SYSTEMS-1 Complete notes examples
 
GDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentationGDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentation
 
Arduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.pptArduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.ppt
 
Heart Disease Prediction using machine learning.pptx
Heart Disease Prediction using machine learning.pptxHeart Disease Prediction using machine learning.pptx
Heart Disease Prediction using machine learning.pptx
 
Past, Present and Future of Generative AI
Past, Present and Future of Generative AIPast, Present and Future of Generative AI
Past, Present and Future of Generative AI
 
Internship report on mechanical engineering
Internship report on mechanical engineeringInternship report on mechanical engineering
Internship report on mechanical engineering
 
Introduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptxIntroduction-To-Agricultural-Surveillance-Rover.pptx
Introduction-To-Agricultural-Surveillance-Rover.pptx
 

DIGITAL DESIGN

  • 2. Numbering System The number system is used for representing the information. The number system has different bases and the most common of them are the decimal, binary, octal, and hexadecimal. The base or radix of the number system is the total number of the digit used in the number system. If the number system representing the digit from 0 – 9 then the base of the system is the 10.
  • 3. Types of Number Systems
  • 4. Decimal Number System The number system is having digit 0, 1, 2, 3, 4, 5, 6, 7, 8, 9; The base of a system, more properly called the RADIX, is the number of different values that can be expressed using a single digit. When writing a number, the digits used give its value, but the number is scaled by its RADIX POINT. For example, 456.210 is ten times bigger than 45.6210 although the digits are the same.
  • 5. Binary Number System Binary has only two values 0 and 1. If larger values than 1 are needed, extra columns are added to the left. Each column value is now twice the value of the column to its right. For example the decimal value three is written 11 in binary (1 two + 1 one). The digital electronic equipment's are works on the binary number system and hence the decimal number system is converted into binary system.
  • 6. Octal Number System Octal has eight values 0 to 7. If larger values than 7 are needed, extra columns are added to the left. The octal system has the base of eight as it uses eight digits 0, 1, 2, 3, 4, 5, 6, 7. The next digit in the octal number is represented by 10, 11, 12, which are equivalent to decimal digits 8, 9, 10 respectively. The main advantage of using octal number system is that it can be converted directly to binary in a very easy manner.
  • 7. Hexadecimal Number System • The hexadecimal number system has a base of 16, and hence it consists of the following sixteen number of digits. • 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. • This Hexadecimal system is used in computer registers to store the addresses of the data. If we have to give a large number of binary strings. • For suppose 1011110110001011111010110001101, it is very much difficult and create a lot of confusion. So computer uses Hexadecimal numbers in representation of such strings.
  • 8. Number System Conversions Any radix to Decimal number system D= 𝑖=−𝑛 𝑝−1 𝑑𝑖. 𝑟 𝑖 . Where p is No. of digits to the left of the radix point. n is No. of digits to the right of the radix point. d is value of the number. r is radix of the number system. The number based conversions are essential in digital electronics. Why because, in all digital system, we have the input in decimal format. While computation system need binary conversion and result will be Hexadecimal format by inverse conversion.
  • 9. Hexadecimal to binary conversion To convert a hexadecimal number to a binary number, convert each hexadecimal digit to its four digit equivalent. For example, consider the hexadecimal number 9AF which is converted into a binary digit. The conversions are explained below.
  • 10. Binary to Hexadecimal conversion To convert the given binary number into its equivalent hexadecimal number rewrite the binary number of the sets of four digits. Then place the hexadecimal digit in front of each four digit set of a binary number as explained by the following number.
  • 11. Hexadecimal to Decimal conversion The base of the hexadecimal number system is 16, therefore the weights corresponding to various positions of the digits will be as shown below. For instance, consider the conversion of hexadecimal number E8F6.27 into its equivalent binary number.  Therefore E8f6.27 written in decimal as 59638.1523437.
  • 12. Decimal to Hexadecimal conversion The conversion of the given decimal number into hexadecimal number requires the application of hex-dabble method. Consider the conversion of the decimal number 3749 into its hexadecimal equivalent number. The third reminder 13 is equivalent to D in a hexadecimal number system. Thus the equivalent hexadecimal number D97.
  • 14. Number System Conversions Binary to Decimal: (1010.01)2 1×23 + 0x22 + 1×21+ 0x20 + 0x2 -1 + 1×2 -2 = 8+0+2+0+0+0.25 = 10.25 (1010.01)2 = (10.25)10  Decimal to Octal (10.25)10 (10)10 = (12)8 ; And Fractional part:0.25 x 8 = 2.00 (10.25)10 = (12.2)8
  • 15. Number System Conversions  Octal to Decimal (12.2)8 1 x 81 + 2 x 80 +2 x 8-1 = 8+2+0.25 = 10.25 (12.2)8 = (10.25)10 Hexadecimal to octal Number First the individual digits are converted into its binary bits. After that the subsequent bits are grouped into 3 bits. (ABCD)16 A (1010) , B (1011), C (1100), D(1101) 001 010 101 111 001 101 (pairing 3 binary bits) So, (ABCD)16 =(125715)8
  • 16. Signed Magnitude Representation MSB of a bit string is used as the sign bit and the lower bits contain the magnitude. Ex: (1111)2= (15)10 unsigned number representation. (01111)2= +(15)10 (11111)2= −(15)10 signed number representation. Range of the n bit signed magnitude integer is given as - (2 𝑛−1 -1) to + (2 𝑛−1 -1) to
  • 17. Complement of Numbers There are two types of complements for each base-r system. 1. r's complement , 2. (r -1)'s complement. Ex: The 9’s complement of 546700 is 999999-546700=453299 For binary numbers, r = 2 and r –1 = 1, so the 1's complement of N is (2^n -1) –N. Ex: The 1’s complement of 1011000is 0100111.
  • 18. Complement of Numbers Radix Complement The r's complement of an n-digit number N in base r is defined as 𝑟 𝑛–N for N ≠ 0 and as 0 for N = 0. Comparing with the (r -1) 's complement, we note that the r’s complement is obtained by adding 1 to the (r-1) 's complement, since 𝑟 𝑛–N = [(𝑟 𝑛-1)–N] + 1. Ex: The 10's complement of 012398 is 987602 Ex: The 2's complement of 1101100 is 0010100
  • 19. Compliment of Numbers The subtraction of two n-digit unsigned numbers M –N in base r can be done as follows:
  • 20. Compliment of Numbers Using 10's complement, subtract 72532 –3250. Using 10's complement, subtract 3250 –72532 Here no end carry, Therefore, the answer is –(10's complement of 30718) is - 69282.
  • 21. CODES In the coding, when numbers or letters are represented by a specific group of symbols, that group of symbols is called as code or Binary code. If the code has positional weights, then it is said to be weighted code. Otherwise, it is an unweighted code. Codes are required to conveniently input data into digital system and interpret results.
  • 23. CODES Weighted codes: In weighted codes, each digit is assigned a specific weight according to its position. For example, in 8421BCD code, 1001 the weights of 1, 0, 0, 1 (from left to right) are 8, 4, 2 and 1 respectively. The codes 8421BCD, 2421BCD, 5211BCD are all weighted codes. Non-weighted codes: The non-weighted codes are not positionally weighted. In other words, each digit position within the number is not assigned a fixed value ( or weight ). Excess-3 and gray code are non-weighted codes.
  • 24. CODES Reflective codes: A code is reflective when the code is self complementing. In other words, when the code for 9 is the complement the code for 0, 8 for 1, 7 for 2, 6 for 3 and 5 for 4. 2421BCD, 5421BCD and Excess-3 code are reflective codes.  Sequential codes: In sequential codes, each succeeding code is one binary number greater than its preceding code. This property helps in manipulation of data. 8421 BCD and Excess-3 are sequential codes.
  • 25. CODES Alphanumeric codes: Codes used to represent numbers, alphabetic characters, symbols and various instructions necessary for conveying intelligible information. ASCII, EBCDIC, UNICODE are the most-commonly used alphanumeric codes.  Error detecting and correcting codes: Codes which allow error detection and correction are called error detecting and correcting codes. Hamming code is the mostly commonly used error detecting and correcting code.
  • 26. Binary Coded Decimal(BCD) Code In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express each of the decimal digits with a binary code. In the BCD, with four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD. Ex: (874)10= (1000 0111 0100) 𝑏𝑐𝑑
  • 27. Excess-3 Code • It is non-weighted code used to express decimal numbers. The Excess-3 code words are derived from the 8421 BCD code.
  • 28. Gray Code It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the bit position. It has a very special feature that, only one bit will change each time. the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation. For Low power applications Gray code will be useful.
  • 29. Codes Conversion There are many methods or techniques which can be used to convert code from one format to another. We'll demonstrate here the following. 1.Binary to BCD Conversion 2.BCD to Binary Conversion 3.BCD to Excess-3 4.Excess-3 to BCD
  • 30. Binary to BCD conversion Step 1 -- Convert the binary number to decimal. Step 2 -- Convert decimal number to BCD. • Ex: binary number is (11101)2 • Binary Number −> (11101)2 = Decimal Number −> (29)10 (29)10 =(00101001)BCD
  • 31. BCD to Binary conversion Step 1 -- Convert the BCD number to decimal. Step 2 -- Convert decimal to binary. Ex: convert (00101001)BCD to Binary. (00101001)BCD => 00102 10012 => 210 910 => Decimal Number −> (29)10 Decimal Number −> 2910 = Binary Number −> (11101)2
  • 32. BCD to Excess-3 conversion Step 1 -- Convert BCD to decimal. Step 2 -- Add (3)10 to this decimal number. Step 3 -- Convert into binary to get excess-3 code. Ex: convert (1001)BCD to Excess-3. Step 1 − Convert to decimal (1001)BCD = 910 Step 2 − Add 3 to decimal (9)10 + (3)10 = (12)10 Step 3 − Convert to Excess-3 (12)10 = (1100)2
  • 33. Excess-3 to BCD conversion • Step 1 -- Subtract (0011)2 from each 4 bit of excess-3 digit to obtain the corresponding BCD code. Ex: convert (10011010)XS-3 to BCD. Ex-3 -> 1001 1010 subtract (0011)2 -> 0011 0011 result BCD -> 0110 0111 (10011010)XS-3 = (01100111)BCD
  • 34. Binary to Gray Conversion The first bit(MSB) of the gray code is the same as the first bit of the binary number The second bit of the gray code equals the exclusive OR of the first and second bits of the binary number from MSB The third bit of the gray code equals the exclusive OR of the second and third bits of the binary number and so on.  Ex: (01001)2= (01101) gray
  • 35. Gray to Binary Conversion The M.S.B of the binary number will be equal to the M.S.B of the given gray code. Now if the second gray bit is 0 the second binary bit will be same as the previous or the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it was 0 it will be 1. This step is continued for all the bits to do Gray code to binary conversion.  Ex: (01101) gray = (01001)2
  • 36. UNIVERSEL GATES  A Gate which can be use to create any Logic Gate is called Universal Gate.  NAND and NOR Gates are called Universal Gates because all the other Gates can be created by using these Gates.  NAND and NOR Gates can implement any logical Boolean expression.  In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families.
  • 37. NAND Gate NAND function is compliment of the AND function. NAND consist of an AND graphic symbol followed by a small circle.  Its name is an abbreviation of NOT AND . NAND output logical expression is given as z = 𝑥. 𝑦 x y z 0 0 1 0 1 1 1 0 1 1 1 0 x y z Truth table for NAND Gate Fig:Logic symbol for NAND Gate
  • 38. Inverter implementation by NAND Gate All NAND input pins connect to the input signal A gives an output 𝐴. One NAND input pin is connected to the input signal A while all other input pins are connected to logic 1. The output will be 𝐴. A 𝐴 𝐴 A 1 A ~A 0 1 1 0 Truth table for NOT Gate Fig: NOT Gate implementation by NAND Gate
  • 39. AND Gate implementation by NAND Gate The AND is replaced by a NAND gate with its output complemented by a NAND gate inverter . A 𝑨. 𝑩 Truth table for AND Gate Fig:AND Gate implementation by NAND Gate A B 𝑨. 𝑩 A B A.B 0 0 0 0 1 0 1 0 0 1 1 1
  • 40. OR Gate implementation by NAND Gate The OR gate is replaced by a NAND gate with all its inputs complemented by NAND gate inverters . Truth table for OR Gate Fig:OR Gate implementation by NAND Gate A B A B A+B 0 0 0 0 1 1 1 0 1 1 1 1 𝑨 𝑩 𝑨. 𝑩
  • 41. NOR Gate implementation by NAND Gate A NOR gate is simply an OR gate with an inverted output: Truth table for NOR Gate Fig:NOR Gate implementation by NAND Gate A B Q=𝑥 + 𝑦 0 0 1 0 1 0 1 0 0 1 1 0
  • 42. XOR Gate implementation by NAND Gate The output of an XOR gate is true only when one of its inputs is true.  If both of an XOR gate's inputs are false, or if both of its inputs are true, then the output of the XOR gate is false. Logical symbol is given as Truth table for XOR Gate Fig:XOR Gate implementation by NAND Gate A B Q= 0 0 0 0 1 1 1 0 1 1 1 0 A ⊕ B
  • 43. XNOR Gate implementation by NAND Gate The output of an XNOR gate is true when all of its inputs are true or when all of its inputs are false.  If some of its inputs are true and others are false, then the output of the XNOR gate is false.  Logical symbol is given like Truth table for XNOR Gate Fig: XNOR Gate implementation by NAND Gate A B Q= 0 0 1 0 1 0 1 0 0 1 1 1 A B 𝐴 ⊕ 𝐵 𝐴 ⊕ 𝐵
  • 44. NOR Gate NOR function is compliment of the AND function. NOR consist of an OR graphic symbol followed by a small circle.  Its name is an abbreviation of NOT OR . NOR output logical expression is given as z = 𝑥 + 𝑦 x y z 0 0 1 0 1 0 1 0 0 1 1 0 x y z Truth table for NOR Gate Fig: Logic symbol for NOR Gate
  • 45. Inverter implementation by NOR Gate All NOR input pins connect to the input signal A gives an output 𝐴. One NOR input pin is connected to the input signal A while all other input pins are connected to logic 0. The output will be 𝐴. Fig: NOT Gate implementation by NOR Gate
  • 46. AND Gate implementation by NOR Gate An AND gate gives a 1 output when both inputs are 1; a NOR gate gives a 1 output only when both inputs are 0.  Therefore, an AND gate is made by inverting the inputs to a NOR gate Truth table for AND Gate Fig: AND Gate implementation by NOR Gate A B Q=A.B 0 0 0 0 1 0 1 0 0 1 1 1
  • 47. OR Gate implementation by NOR Gate The OR gate is simply a NOR gate followed by a NOT gate. Truth table for OR Gate Fig: OR Gate implementation by NOR Gate A B Q= A+B 0 0 0 0 1 1 1 0 1 1 1 1
  • 48. NAND Gate implementation by NOR Gate A NAND gate is made using an AND gate in series with a NOT gate A B Q=𝐴. 𝐵 0 0 1 0 1 1 1 0 1 1 1 0Truth table for NAND Gate Fig: NAND Gate implementation by NOR Gate
  • 49. XOR Gate implementation by NOR Gate An XOR gate is made by connecting the output of 3 NOR gates.  This expresses the logical formula (A AND B) NOR (A NOR B). This construction require a propagation delay three times that of a single NOR gate and uses five gates. Logical symbol is given as Truth table for XOR Gate Fig:XOR Gate implementation by NOR Gate A B Q= 0 0 0 0 1 1 1 0 1 1 1 0 A ⊕ B
  • 50. XNOR Gate implementation by NOR Gate An XNOR gate can be constructed from four NOR gates implementing the expression (A NOR N) NOR (B NOR N) where N = A NOR B. This construction entails a propagation delay three times that of a single NOR gate and uses four gates. Logical symbol is given as Truth table for XNOR Gate Fig:XNOR Gate implementation by NOR Gate A B Q= 0 0 1 0 1 0 1 0 0 1 1 1 𝐴 ⊕ 𝐵
  • 51. Canonical and Standard forms In Boolean algebra, Boolean function can be expressed as Canonical Disjunctive Normal Form known as minterm . And some are expressed as Canonical Conjunctive Normal Form known as maxterm . minterm for each combination of the variables that produces a 1 in the function and then taking the OR of all those terms. maxterm for each combination of the variables that produces a 0 in the function and then taking the AND of all those terms Boolean functions expressed as a sum of minterms(SOP) or product of maxterms(POS) are said to be in canonical form.
  • 52. Truth table Notation for Minterms and Maxterm • Example: Assume 3 Literals x,y,z .
  • 53. Sum of minterm With ‘n’ variable, maximum possible minterms are 2^n. Ex: Express the Boolean function F = A + B’C as a sum of minterms. • First term A = A(B + B’) = AB + AB’ A = AB(C + C’) + AB'(C + C’) = ABC + ABC’+ AB’C + AB’C’ • second term B’C = B’C(A + A’) = AB’C + A’B’C F = A + B’C = ABC + ABC’ + AB’C + AB’C’ + A’B’ here AB’C appears twice, from Boolean theorems F = A’B’C + AB’C + AB’C + ABC’ + ABC= m1 + m4 + m5 + m6 + m7 SOP is represented as ∑1, 4, 5, 6, 7) .
  • 54. Product of maxterm Ex: Express the Boolean function F = xy + x’z as a product of maxterms sol: F = xy + x’z = (xy + x’)(xy + z) = (x + x’)(y + x’)(x + z)(y + z) = (x’ + y)(x + z)(y + z) x’ + y = x’ + y + zz’ = (x’+ y + z)(x’ + y + z’) x + z = x + z + yy’ = (x + y + z)(x + y’ + z) y + z = y + z + xx’ = (x + y + z)(x’ + y + z) F = (x + y + z)(x + y’ + z)(x’ + y + z)(x’ + y + z’) = M0*M2*M4*M5 POS is represented as ∏(0, 2, 4, 5) With ‘n’ variable, maximum possible maxterms are 2^n.
  • 55. Conversion between canonical Forms Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the original form with those that do not. Example: f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’ = m1 + m2 + m4 + m6 = ∑(1,2,4,6) = ∏(0,3,5,7) = (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
  • 56. Standard Forms Standard forms are like canonical forms, except that not all variables need appear in the individual product (SOP) or sum (POS) terms. Example: f1(a,b,c) = a’b’c + bc’ + ac’ is a standard sum-of-products form f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’) is a standard product-of-sums form.
  • 57. Conversion of SOP from standard to canonical form Expand non-canonical terms by inserting equivalent of 1 in each missing variable x: (x + x’) = 1 Remove duplicate minterms f1(a,b,c) = a’b’c + bc’ + ac’ = a’b’c + (a+a’)bc’ + a(b+b’)c’ = a’b’c + abc’ + a’bc’ + abc’ + ab’c’ = a’b’c + abc’ + a’bc + ab’c’
  • 58. Conversion of POS from standard to canonical form Expand noncanonical terms by adding 0 in terms of missing variables (e.g., xx’ = 0) and using the distributive law Remove duplicate maxterms f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’) = (a+b+c)•(aa’+b’+c’)•(a’+bb’+c’) = (a+b+c)•(a+b’+c’)•(a’+b’+c’)• (a’+b+c’)•(a’+b’+c’) = (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)