This document summarizes the topics covered in session 20 of the CS304PC course on computer organization and architecture. It discusses multiplication algorithms, including unsigned binary multiplication using shifting and adding of partial products, and signed (2's complement) multiplication using the Booth algorithm. It also describes array multipliers which generate all product bits simultaneously using a combinational circuit rather than sequential addition and shifting. The next session will cover computer division algorithms.

1. CS304PC:Computer Organization
and Architecture (R18 II(I sem))
Department of computer science and engineering
(AI/ML)
Session 20
by
Asst.Prof.M.Gokilavani
VITS
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2. TEXTBOOK:
• 1. Computer System Architecture – M. Moris Mano, Third Edition,
Pearson/PHI.
REFERENCES:
• Computer Organization – Car Hamacher, Zvonks Vranesic, Safea
Zaky, Vth Edition, McGraw Hill.
• Computer Organization and Architecture – William Stallings Sixth
Edition, Pearson/PHI.
• Structured Computer Organization – Andrew S. Tanenbaum, 4th
Edition, PHI/Pearson.
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3. Unit III
Data Representation: Data types ,Complements, fixed point
Representations, Floating point representation.
Computer Arithmetic: Addition and subtraction,
multiplication Algorithms, Division Algorithms, Floating-point
Arithmetic operations, Decimal Arithmetic unit, Decimal
Arithmetic operations.
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4. Topics covered in session 20
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• Addition and subtraction
• Multiplication Algorithms
• Division Algorithms
• Floating-point Arithmetic operations
• Decimal Arithmetic unit
• Decimal Arithmetic operations.

5. Multiplication Algorithm
• Example:
• In multiplication algorithm, successive bits of the multiplier, least significant bit
first.
• If the multiplier bit is a 1, the multiplicand is copied down, otherwise zero are
copied down.
• The numbers copied down is successive lines are shifted one position to the left
from the previous number. Finally, the numbers are added, and their sum forms the
product.
• The sign of the product is determined from the sign of the multiplicand and
multiplier.
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6. Multiplication Algorithm
• The multiplier and multiplicand bits are loaded into two registers Q
and M. A third register A is initially set to zero.
• C is the 1-bit register which holds the carry bit resulting from addition.
Now, the control logic reads the bits of the multiplier one at a time.
• If Q is 1, the multiplicand is added to the register A and is stored back
in register A with C bit used for carry.
• Then all the bits of CAQ are shifted to the right 1 bit so that C bit goes
to A , A0 goes to Q and Q is lost.
• If Q is 0, no addition is performed just do the shift. The process is
repeated for each bit of the original multiplier.
• The resulting 2n bit product is contained in the QA register.
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8. Unsigned Binary Multiplication
There are three types of operation for multiplication.
• It should be determined whether a multiplier bit is 1 or 0 so that
it can designate the partial product.
• If the multiplier bit is 0, the partial product is zero; if the
multiplier bit is 1, the multiplicand is partial product.
• It should shift partial product.
• It should add partial product.
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11. Alternative Method for Unsigned Binary
Multiplication
Algorithm
• Step 1: Clear the sum (accumulator A). Place the multiplicand in X
and multiplier in Y.
• Step 2: Test Y ; if it is 1, add content of X to the accumulator A.
• Step 3: Logical Shift the content of X left one position and content of
Y right one position.
• Step 4: Check for completion; if not completed, go to step 2
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14. Signed Multiplication (Booth Algorithm) – 2’s
Complement Multiplication
• Multiplier and multiplicand are placed in Q and M register respectively.
• There is also one bit register placed logically to the right of the least
significant bit Q of the Q register and designated as Q .
• The result of multiplication will appear in A and Q resister.
• A and Q are initialized to zero if two bits (Q and Q ) are the same (11 or 00)
then all the bits of A, Q and Q registers are shifted to the right 1 bit.
• If the two bits differ then the multiplicand is added to or subtracted from the
A register depending on weather the two bits are 01 or 10.
• Following the addition or subtraction the arithmetic right shift occurs.
• When count reaches to zero, result resides into AQ in the form of signed
integer [-2 *a + 2 *a + …………… + 2 *a + 2 *a ].
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17. Array Multiplier
• Checking the bits of the multiplier one at a time and forming partial
products is a sequential operation that requires a sequence of add and
shift micro operations.
• The multiplication of two binary numbers can b done with one micro
operation by means of a combinational circuit that forms the product
bits all at once.
• An array multiplier requires a large number of gates, and integrated
circuits.
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18. Array Multiplier
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21. Topics to be covered in next session 21
• Division Algorithm
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Thank you!!!