CS304PC:Computer Organization and Architecture Session 19 Addition and subtraction algorithm

1. CS304PC:Computer Organization
and Architecture (R18 II(I sem))
Department of computer science and engineering
(AI/ML)
Session 19
by
Asst.Prof.M.Gokilavani
VITS
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2. TEXTBOOK:
• 1. Computer System Architecture – M. Moris Mano, Third Edition,
Pearson/PHI.
REFERENCES:
• Computer Organization – Car Hamacher, Zvonks Vranesic, Safea
Zaky, Vth Edition, McGraw Hill.
• Computer Organization and Architecture – William Stallings Sixth
Edition, Pearson/PHI.
• Structured Computer Organization – Andrew S. Tanenbaum, 4th
Edition, PHI/Pearson.
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3. Unit III
Data Representation: Data types ,Complements, fixed point
Representations, Floating point representation.
Computer Arithmetic: Addition and subtraction,
multiplication Algorithms, Division Algorithms, Floating-point
Arithmetic operations, Decimal Arithmetic unit, Decimal
Arithmetic operations.
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4. Topics covered in session 19
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• Addition and subtraction
• Multiplication Algorithms
• Division Algorithms
• Floating-point Arithmetic operations
• Decimal Arithmetic unit
• Decimal Arithmetic operations.

5. Introduction
• Arithmetic instructions in digital computer manipulate data to produce
results for computational problems. The four basic arithmetic
operations are addition , subtraction, multiplication and division.
• The solution to any problem that is stated by a finite number of well-
defined procedural steps is called an algorithm.
• Various arithmetic algorithms and show the procedure for
implementing them in digital hardware.
• Types of data are
• Fixed point binary data in signed magnitude representation
• Fixed point binary data in signed 2’s complement
representation
• Floating point binary data
• Binary coded decimal (BCD) data
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6. Addition and Subtraction algorithm
• There are three ways of representing negative fixed-point binary
number:
• Signed-magnitude
• Signed 1’s complement
• Signed 2’s complement
• For floating point operation most computers use the signed-
magnitude representation.
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7. Addition and subtraction with signed-
magnitude data
• Addition and subtraction algorithm
• when the signs of A and B are identical (different), add the two
magnitude and attached the sign of A to the result.
• When the sign of A and B are different (identical, compare the
magnitude and subtract the smaller number from the larger.
• Choose the sign of the result to be same as A if A ˃ B or the
complement of the sign of A if A ˂ B.
• If the magnitude are equal, Subtract B from A and make the sign of
the result positive.
Note: The procedure for identical signs in addition algorithm is same as
for different sign in subtraction algorithm.
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9. Hardware Implementation
• To implement the two-arithmetic operation with hardware, it is
necessary that the two numbers be stored in register.
• Let A and B be two register that holds the magnitude of the
numbers, and A1 and B1 be two flip-flop that holds the
corresponding signs.
• The result of the operation is transfer to third register.
• In hardware implementation,
• First, a parallel-adder is needed to perform the
microoperation A+B.
• Second a comparator circuit is needed to establish if A ˃
B, A = B, or A ˂ B.
• Third two parallel-subtractor circuits are needed to
perform the micro-operations A –B and B –A.
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11. Working of Hardware Implementation
• It consists of register A and B and sign flip-flop A1 and B1.
• Subtraction is done by adding A and 2’s complement of B.
• The output carry is transferred to flip-flops E, where it can be
checked to determine to relative magnitude of the two
numbers.
• The add overflow flip-flop AVF holds the overflow bit when A
and B are added.
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12. Working of Hardware Implementation
Addition of A and B is done through the parallel adder (consists of full-
adder).
• The S (Sum) output of the adder is applied to the input of the A
register.
• The complementor (consists of ex-OR gates ) provides an output of
B or the complement of B depending on the state of the mode
control M.
• When M=0, the output of B is transferred to the adder, the input
carry is 0, and the output of the adder is equal to the sum A+B.
• When M=1, the 1’s complement of B is applied to the adder, the
input carry is 1 and output S=A+B+1.
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14. Addition and Subtraction with 2’s complement data
• The leftmost bit of a binary number represent the sign bit :
• 0 for positive
• 1 for negative
• If the sign bit is 1, the entire number is represented in 2’s complement
form.
• The addition of two number is signed complement form consists of
adding the numbers with the sign bits treated the same as the order bits
of the number.
• A carry-out of the sign-bit position is discarded. The subtraction
consists of first taking 2’s complement of the subtrahend and then
adding it to be minuend.
• When overflow is detected when the output of the gate is equal to 1.
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17. Topics to be covered in next session 20
• Multiplication Algorithm
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Thank you!!!