SPICE MODEL of SSM3K7002FU (Professional+BDP Model) in SPICE PARK

Device Modeling Report

COMPONENTS: Power MOSFET (Professional Model)
PART NUMBER: SSM3K7002FU
MANUFACTURER: TOSHIBA
Body Diode (Professional Model) / ESD Protection

Bee Technologies Inc.

.

All Rights Reserved Copyright (C) Bee Technologies Inc. 2006

MOSFET MODEL PARAMETERS

PSpice model
Model description
parameter
LEVEL
L Channel Length
W Channel Width
KP Transconductance
RS Source Ohmic Resistance
RD Ohmic Drain Resistance
VTO Zero-bias Threshold Voltage
RDS Drain-Source Shunt Resistance
TOX Gate Oxide Thickness
CGSO Zero-bias Gate-Source Capacitance
CGDO Zero-bias Gate-Drain Capacitance
CBD Zero-bias Bulk-Drain Junction Capacitance
MJ Bulk Junction Grading Coefficient
PB Bulk Junction Potential
FC Bulk Junction Forward-bias Capacitance Coefficient
RG Gate Ohmic Resistance
IS Bulk Junction Saturation Current
N Bulk Junction Emission Coefficient
RB Bulk Series Resistance
PHI Surface Inversion Potential
GAMMA Body-effect Parameter
DELTA Width effect on Threshold Voltage
ETA Static Feedback on Threshold Voltage
THETA Mobility Modulation
KAPPA Saturation Field Factor
VMAX Maximum Drift Velocity of Carriers
XJ Metallurgical Junction Depth
UO Surface Mobility


Transconductance Characteristic

Circuit Simulation Result

0.5
Measurement
0.45 Simulation

0.4
Transconductance Gfs(s)

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0
0 50 100 150 200
Drain current ID (mA)

Comparison table

Gfs(S)
Id(mA) Error(%)
Measurement Simulation
10 0.1 0.098039216 -1.96
20 0.133 0.137931034 3.71
50 0.208 0.217391304 4.52
100 0.31 0.307692308 -0.74
200 0.43 0.434782609 1.11


Vgs-Id Characteristic

Circuit Simulation result

800mA

0A
0V 1.0V 2.0V 3.0V 4.0V 5.0V
I(V2)
V_VGS

Evaluation circuit

V2

U1
SSM3K7002FU
VDD
10Vdc

VGS
0Vdc

0 0 0


Comparison Graph


200

180 Measurement
Simulation
160

140
Drain current ID(mA)

120

100

80

60

40

20

0
0 1 2 3
Gate-Source voltage VGS (V)

Simulation Result

VGS(V)
ID(mA) Error (%)
2 1.55 1.61 3.87
5 1.65 1.67 1.21
10 1.72 1.73 0.58
20 1.83 1.82 -0.55
50 2.00 1.99 -0.50
100 2.17 2.18 0.46
200 2.45 2.46 0.41


Rds(on) Characteristic


500mA

400mA

300mA

200mA

100mA

0A
0V 0.5V 1.0V 1.5V 2.0V
I(V2)
V_VDD

Evaluation circuit

V2

U1
SSM3K7002FU
VDD
10Vdc

VGS
10Vdc

0 0 0

Simulation Result

ID=500mA,
Measurement Simulation Error (%)
VGS=10V
R DS (on) 2.0  2.0  0.0


Gate Charge Characteristic

6.0V

5.0V

4.0V

3.0V

2.0V

1.0V

0V
0 0.2n 0.4n 0.6n 0.8n 1.0n 1.2n 1.4n
V(W1:3)
Time*1mA

Evaluation circuit

Vsense

U1
SSM3K7002FU I1
D1
Dbreak 0.2Adc

W1
+

-
I2 W VD
ION = 0A 30Vdc
IOFF = 1.1mA

0

Simulation Result

VDD=30V,
ID= 200mA Measurement Simulation Error (%)
,VGS=5V
Qgs 0.280 nC 0.2795 nC -0.18
Qgd 0.236 nC 0.234 nC -0.85
Qg 1.000 nC 1.011 nC 1.10


Gate Charge Characteristic Reference

VGS-Qg

7
VDD=30V
6
5
VGS (V)

4
3
2
1
0
0 0.5 1 1.5
Qg (nC)


Capacitance Characteristic

Measurement
Simulation

Simulation Result

Cbd(pF)
VDS(V) Error(%)
0.1 20 19.87 -0.65
0.2 19 19.07 0.37
0.5 17 17.15 0.88
1 15 14.946 -0.36
2 12.3 12.315 0.12
5 8.8 8.82 0.23
10 6.5 6.58 1.23
20 4.8 4.815 0.31
50 3.1 3.15 1.61


Switching Time Characteristic


12V

11V
10V

9V

8V

7V
6V

5V

4V

3V

2V

1V
0V
0.98us 1.00us 1.02us 1.04us 1.06us 1.08us
V(2) V(3)/3
Time

Evaluation circuit

Vsense RL
3
150

U1
R1 SSM3K7002FU
V1 = 0 2
VD
50
V2 = 20 30Vdc

TD = 1u V1
R2
TR = 10n
50
TF = 10n

PW = 5u

PER = 10u
0

Simulation Result

ID=0.2A,
VDD= 30V, Measurement Simulation Error(%)
VGS=0/10V
Td(on) 2.400 ns 2.397 ns -0.13


Output Characteristic


10 7 5 4.5 4 3.3
500mA

3.0 V
400mA

2.7 V
300mA

2.5V
200mA

100mA
VGS= 2.3V

0A
0V 0.5V 1.0V 1.5V 2.0V
I(V2)
V_VDD

Evaluation circuit

V2

U2
SSM3K7002FU
VDD
10Vdc

VGS
10Vdc

0 0


Forward Current Characteristic


1.0A

0.9A

0.8A

0.7A

0.6A

0.5A

0.4A

0.3A

0.2A

0.1A

0A
0V -0.2V -0.4V -0.6V -0.8V -1.0V -1.2V -1.4V
I(V2)
V_VDS

Evaluation Circuit

V2

SSM3K7002FU
VDS
0Vdc

VGS
0Vdc

0


Comparison Graph


0.9
Measurement
0.8 Simulation

0.7
Drain reverse current IDR(mA)

0.6

0.5

0.4

0.3

0.2

0.1

0
0 0.2 0.4 0.6 0.8 1 1.2
Source-Drain voltage VSD(V)

Simulation Result

VSD(V)
IDR(A) %Error
0.05 0.75 0.757 0.93
0.1 0.8 0.803 0.38
0.2 0.87 0.866 -0.46
0.5 1.02 1.007 -1.27
0.8 1.12 1.129 0.80


Reverse Recovery Characteristic


400mA

300mA

200mA

100mA

-0mA

-100mA

-200mA

-300mA

-400mA
14.96us 15.00us 15.04us 15.08us 15.12us
I(R1)
Time

Evaluation Circuit

R1

50
V1 = -9.5V

V2 = 10.8

TD = 2ns V1 D3K7002FU_PRO
U2
TR = 10n

TF = 10n

PW = 15us

PER = 100us

0

Compare Measurement vs. Simulation

Measurement Simulation Error (%)
trj 17.000 ns 16.911 ns -0.524
trb 24.000 ns 24.091 ns 0.379
trr 41.000 ns 41.002 ns 0.005


Reverse Recovery Characteristic Reference

Trj=17 (ns)
Trb=24(ns)
Conditions:Ifwd=lrev=0.2(A),Rl=50

Example

Relation between trj and trb


Zener Voltage Characteristic

10mA

9mA

8mA

7mA

6mA

5mA

4mA

3mA

2mA

1mA

0A
0V 5V 10V 15V 20V 25V 30V 35V 40V 45V 50V
I(V2)
V_VGS

Evaluation Circuit

U1
V2 SS M3K 70 02FU
ID

0A dc

VG S
0V dc

0


Zener Voltage Characteristic Reference


SPICE MODEL of SSM3K7002FU (Professional+BDP Model) in SPICE PARK

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