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1
2
3
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
Receiver
2
3
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
Transmitter
1
2
3
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
Receiver
2
3
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
Transmitter
1
2
3
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
Receiver
2
3
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
Transmitter
1
2
3
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
Receiver
2
3
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
Transmitter
- BPSK
- QPSK
- M-ary QAM
1
2
3
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
Receiver
2
3
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
Transmitter
- BPSK
- QPSK
- M-ary QAM
1
2
3
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
Receiver
2
3
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
Transmitter
- BPSK
- QPSK
- M-ary QAM
1
2
3
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
Receiver
2
3
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
Transmitter
- BPSK
- QPSK
- M-ary QAM
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
N >> 1
M >> 1
Receiver
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
N >> 1
M >> 1
Receiver
d
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
Receiver
d
1m
N=20, Fc=3GHz
N=400, Fc=60GHz
Fc= sub-6GHz
(e.g., LTE)
2
N
1
Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
LNA DC A/D
LNA DC A/D
DSP Dig
Receiver
N >> 1
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
Receiver
Fc= mmWave
(e.g., 60GHz)
N >> 1
M >> 1
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
Receiver
Fc= mmWave
(e.g., 60GHz)
N >> 1
M >> 1
Receiver
DSP: Speed
Interface: DSP to A/D (D/A)
A/D: Resolution
Sampling rate
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
Receiver
DSP: Speed
Interface: DSP to A/D (D/A)
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
Receiver
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
A/D: Resolution
Sampling rate
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
Na
1
2
ASP
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
Receiver
Ma
1
2
ASP
Na << N
Ma << M
2
N
1Dig DSP D/A UC PA
D/A
D/A
UC
UC
PA
PA
···
Transmitter
Na
1
2
ASP
1
2
M
LNA DC A/D
LNA
LNA
DC
DC
A/D
A/D
DSP Dig
···
Receiver
Ma
1
2
ASP
Reason: Na << N
Ma << M
Digitally
controlled
···
ASP
···
···Digitally controlled
switches
Phase shifter (switch) based ASP Designs
+
+
+
+
+
+ +
+
···
···
Low cost
···
ASP
···
···
Best performance
+
+
+
+
+
+
+
+
···
···
Digitally
controlled
···
ASP
···
···Digitally controlled
switches
Phase shifter (switch) based ASP Designs
+
+
+
+
+
+ +
+
···
···
Low cost
···
ASP
···
···
Best performance
+
+
+
+
+
+
+
+
···
···
Digitally
controlled
···
ASP
···
···Digitally controlled
switches
Phase shifter (switch) based ASP Designs
+
+
+
+
+
+ +
+
···
···
Low cost
···
ASP
···
···
Best performance
+
+
+
+
+
+
+
+
···
···
Digitally
controlled
···
ASP
···
···Digitally controlled
switches
Phase shifter (switch) based ASP Designs
+
+
+
+
+
+ +
+
···
···
Low cost
···
ASP
···
···
Best performance
+
+
+
+
+
+
+
+
···
···
Hybrid Analog-Digital Architecture for Massive MIMO: An Introduction

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