UVM RAL is an object-oriented model for registers inside the design. To access these design registers, UVM RAL provides ready-made base classes and APIs

1. Register Abstraction Layer(RAL)
Pushpa

2. Introduction:
• What is RAL?
• TB representation of design registers using UVM register base classes
• Why we need RAL?
• Without register model, there is no way for reference model to get the
expected outputs(reference model does not have enough information to
process the inputs).
• Register model can also be used to implement register access testcases in a
easy manner.
• Configuration of DUT can be implemented easily.
• Register model can also be used in implementing monitor/sb

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• What will be the issue if we don’t have register model?
• Reference model will not be able to predict the expected outputs. so, In that
time sometimes TB may fail.
• For this one alternate solution is there, Don’t implement reg model, directly
refer to design reg by using hierarchal path of the design.
• For this one problem is there, Assume In the design, registers are
implemented wrongly, the mistake is passed.. that problem is not solved in
above solution.. so, this is not good method.. for this only option is RAL.

4. RAL Basics:
• Used to mimic the design register behavior
• Accessible in complete TB by using UVM_config_db/resource_db
• Comes with default testcase implementation in UVM RAL
• Register Layer base classes come with in-built methods, makes it quite easy
to develop tests
• Base classes
• Uvm_reg_field
• Uvm_reg
• Uvm_reg_map
• Uvm_reg_file
• Uvm_reg_block
• Uvm_mem

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• Uvm_reg_field: used for describing the individual reg fields
• Uvm_reg: used for describing the registers
• Uvm_reg_map: used for creating a map where all registers are
mapped.
• Uvm_reg_file:used to group multiple registers into single set
• Uvm_reg_block:used to represent one block of the design(which may
have multiple registers)it also represent multiple blocks together
• Uvm_mem:used to represent the memory eqvivalent representation.
Individual rows of the memory grouping together. multiple such rows
are become uvm_mem.

7. RAL Model Development
• Register model can be developed in two ways
• Manually coding each class
• Script to automate the register model generation(preferred)
• All the companies use automated flow for register model
development
• PERL or Python scripts which takes register definition in XLS or test format,
generates UVM/SV definition of register model.
• Might use IPXACT
• Refer to design specification, List down all the registers, field names,
field width, reset values, access types in to a XLS file.

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• Define all the register definitions using uvm_reg
• Declare all the register fields using uvm_reg_field
• Build methods to create these fields,and configure these fields
• Define reg block using uvm_reg_block
• Instantiate all the registers defined above
• Instantiate uvm_reg_map,for adding all the registers into it.
• Build method for creating registers instances
• Create reg_map instance
• Add all the register with address & access info to reg_map
• Define register adapter class

9. Register Model
• Register model understood in 3 steps
• RAL Model Development
• RAL Base classes, hierarchy
• Base class methods
• RAL model coding for design
• Enabling coverage in RAL
• IP-XACT
• RAL model integration in to TB
• Adapter, sequencer mapping to register map
• Register model instantiation, adding to resource DB.
• RAL model usage in
• Coadding testcases(register access tests, functional tests)
• UVM in built tests for register and memory checks
• Register configuration in functional tests
• Scoreboard and checker implementation
• RAL usage in Verification

10. UVM RAL Model creation involves the below steps
• Writing register classes
• Writing register package
• Instantiation of register classes in register package
• Writing Adapter class
• Integrating register package and adapter in environment
• Accessing registers with RAL

11. Thank You