HELLO

1. Junctionless InGaAs MOSFETs with InAlAs Barrier Isolation
and Channel Thinning by Digital Wet Etching
V. Djara, K. Cherkaoui, T. Lopez, É. O’Connor, I. M. Povey, K. K. Thomas, P. K. Hurley
Tyndall National Institute, University College Cork, “Lee Maltings”, Dyke Parade, Cork, Ireland
E-Mail: vladimir.djara@tyndall.ie / Phone: +353(0)21 234 6227
The junctionless device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al.
in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to
conventional inversion-mode MOSFETs. The objective of this work is to implement the junctionless
device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wide
bandgap In0.52Al0.48As barrier layer. The junctionless device architecture is particularly well suited to
III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a
junctionless MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron
mobility in Si is ~100 cm2
/V.s at Nd = 1 × 1019
/cm3
[2], while that in In0.53Ga0.47As is ~4,000 cm2
/V.s
at a similar Nd level [3]. Moreover, the junctionless architecture circumvents the difficulties
associated with the implantation [4] or regrowth [5] techniques generally used to form the
source/drain (S/D) regions of III-V inversion-mode MOSFETs.
A structure consisting of a 32-nm-thick n-In0.53Ga0.47As (Nd = 2 × 1018
/cm3
) on a 500-nm-thick p-
In0.52Al0.48As (Na = 8 × 1015
/cm3
) barrier was grown by metal organic vapour-phase epitaxy
(MOVPE) on a p+-InP wafer (Fig. 1). The I-V characteristic of the n-In0.53Ga0.47As/p-In0.52Al0.48As
heterojunction diode showed excellent device isolation (Fig. 2). In order to investigate the effect of
channel thickness on the performance of the junctionless devices, we thinned the In0.53Ga0.47As
channel using a 10% H2O2 / 10% HCl digital wet etching process [6]. An etch rate of 0.8 nm/cycle
was extracted from spectroscopic ellipsometry measurements (Fig. 3). The numbers of etch cycles
were adjusted to obtain In0.53Ga0.47As channel thicknesses of 24, 20 and 16 nm. A gate enclosed
device layout [7] was employed to simplify the fabrication process flow (Fig. 4). A surface
passivation in 10% (NH4)2S for 30 min [8] was performed before atomic layer deposition (ALD) of
an 8.5-nm-thick Al2O3 gate oxide. A 200-nm-thick Pd gate was formed by e-beam evaporation and
lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. A 20 sec surface treatment in
10% NH4OH [9] was performed prior to S/D contact formation by e-beam evaporation of a
Au/Ge/Au/Ni/Au stack [10] and lift-off.
Well behaved Id-Vd and Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel
device are shown in Fig. 5 and 6, respectively. The W/L effective of the 60-µm-long annular gate was
calculated using [7] and used to normalize the drain current (Id). A threshold voltage (VT) of -0.51 V
was extracted using the second-derivative method [11]. Fig. 7 compares the Id-Vg characteristics of
devices with 24, 20 and 16-nm-thick In0.53Ga0.47As channels. Scaling the In0.53Ga0.47As channel
thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and
ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a
result, the lowest SS value (115 mV/dec.) was extracted on the 16-nm-thick In0.53Ga0.47As channel
device, but the highest ION/IOFF value (1.5 × 105
) was obtained on the 20-nm-thick In0.53Ga0.47As
channel device (Fig. 8). The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion
near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the
In0.53Ga0.47As bandgap (Fig. 9). Moreover, the conductance analysis yielded low Dit values ranging
from 1.5 × 1012
to 3.5 × 1012
/cm2
.eV (Fig. 10). Based on a flat-band capacitance (CFB) of 0.61
µF/cm2
, obtained from Poisson-Schrödinger simulations, we extracted a flat-band voltage (VFB) of
0.26 V along with an In0.53Ga0.47As Nd of 1.3 × 1018
/cm3
(Fig. 11). The 24 and 20-nm-thick
In0.53Ga0.47As channel devices exhibited an effective mobility (µeff) of 1200 cm2
/V.s at flat band (Fig.
12). The abrupt drop in µeff observed on the 16-nm-thick In0.53Ga0.47As channel device is in agreement
with results reported in [12] for extremely-thin-body In0.53Ga0.47As-on-insulator MOSFETs.
[1] Colinge et al., Nature Nano. 5, 225 (2010). [2] http://www.ioffe.ru. [3] Young et al., J. Cryst. Growth 312,
1546 (2010). [4] Djara et al., Semicond. Sci. Technol. 27, 082001 (2012). [5] Singisetti et al., IEEE Electron
Device Lett. 30, 1128 (2009). [6] Xin Cao et al., Microelectron. Eng. 67, 333 (2003). [7] De Lima et al., IEEE
Trans. Power Electron. 27, 1622 (2012). [8] O’Connor et al., J. Appl. Phys. 109, 024101 (2011). [9] Crook et
al., Appl. Phys. Lett. 91, 192114 (2007). [10] Herbert et al., Microelectron. Eng. 17, 541 (1992). [11] Nazarov et
al., Appl. Phys. Lett. 99, 073502 (2011). [12] Yokoyama et al., IEDM Tech. Dig., 46 (2010).
978-1-4799-0814-1/13/$31.00 ©2013 IEEE 131

2. Fig. 1: Diagram and cross-section transmission
electron microscopy image of the MOVPE
grown n-In0.53Ga0.47As (32 nm)/p-In0.52Al0.48As
(500 nm)/p+
-InP wafer structure.
Fig. 2: I-V characteristic of a
heterojunction diode fabricated on
the wafer structure shown in Fig. 1.
Excellent device isolation obtained.
Fig. 3: In0.53Ga0.47As channel thinning
using a H2O2/HCl digital wet etching
process [6]. An etch rate of 0.8
nm/cycle was obtained.
Fig. 4: Junctionless MOSFET fabrication
process flow: (a) (NH4)2S passivation and ALD
Al2O3, (b) Pd gate lift-off, (c) S/D contact
opening and (d) NH4OH treatment and S/D
contact lift-off.
Fig. 5: Id-Vd characteristic of a
junctionless MOSFET featuring a
24-nm-thick In0.53Ga0.47As channel. A
W/L effective of 7.41 was calculated
using [7].
Fig. 7: Id-Vg characteristics of junctionless
MOSFETs with In0.53Ga0.47As channel
thicknesses ranging from 24 nm to 16 nm
and a W/L effective of 7.41.
Fig. 10: Conductance analysis of a
junctionless MOSFET featuring a 24-
nm-thick In0.53Ga0.47As channel. Dit =
1.5 × 1012
to 3.5 × 1012
/cm2
.eV
extracted for Vg = -0.85 to -1.45 V.
Fig. 12: µeff vs Ns/tInGaAs. A flat-band µeff
of 1200 cm2
/V.s was obtained with tInGaAs
= 24 nm and 20 nm. The abrupt drop in
µeff obtained with tInGaAs = 16 nm is
consistent with [12]. The µeff values were
corrected for RSD.
Fig.9: Cgc-Vg characteristic of a 24-nm-
thick In0.53Ga0.47As channel device
showing low frequency dispersion near
accumulation. The low Cmin of 40 nF/cm2
suggests full depletion at Vg < -1.2 V.
Fig. 11: 100-kHz Cgc-Vg characteristic with
corresponding channel electron density
Ns/tInGaAs, where NS was obtained by
integrating Cgc. Ns/tInGaAs at VFB yielded Nd
= 1.3 × 1018
/cm3
.
Fig. 6: Id-Vg characteristic of a
junctionless MOSFET featuring a 24-
nm-thick In0.53Ga0.47As channel. A VT
of -0.51 V was extracted using the
second-derivative method [11].
Fig. 8: SS, ION/IOFF and RSD vs tInGaAs.
Lowest SS (115 mV/dec.) and highest RSD
(1.8 kΩ) obtained with tInGaAs = 16 nm.
Highest ION/IOFF (1.5 × 105
) obtained with
tInGaAs = 20 nm.
978-1-4799-0814-1/13/$31.00 ©2013 IEEE 132