1. NARASIMHA DHANIREDDY
3142A, Avent Ferry Road, Raleigh – 27606 | Ph: (984)-500-8820 | ndhanir@ncsu.edu
www.linkedin.com/in/narasimhadhanireddy | https://github.com/simha0994
Objective: A highly motivated computer engineering graduate seeking a challenging entry-level position in the field of ASIC design
and verification utilizing strong technical and interpersonal skills.
Education
North Carolina State University, Raleigh, NC Aug’2015 – Dec’2016
• Masters of Science, Computer Engineering; CGPA: 3.714/4
Course work: Architecture of Parallel computers, Digital ASIC design, Computer Networks, ASIC Verification, Embedded
system design, Computer Design and Technology, Object oriented design and development
Vellore Institute of Technology, Vellore, India July’2011 – May’2015
• Bachelor of Technology, Electronics and Communication Engineering; CGPA: 3.89/4
Relevant Course work: Microcontroller and its applications, VLSI system design, Digital logic design, Embedded systems
Skills
• Programming languages: C, C++, Verilog, Ruby, Python, SystemVerilog, Ruby on Rails (Framework)
• Design tools: MATLAB, Keil, Multisim, Proteus, OpenCV, OPNet, ModelSim, CCStudio, SynopsysDC, Git (Version Control)
• OS: Linux, Windows
Projects
Functional Verification of LC3 microcontroller (SystemVerilog)
• Designed a reusable and layered verification environment incorporating generator, driver, scoreboard to verify the
functionality of LC3 microcontroller pipeline in SystemVerilog using a comprehensive instruction set.
• Achieved a functional coverage of 100% with adequate number of constrained random tests and directed test cases.
Design of Bellman-Ford Algorithm using Verilog (Verilog HDL & Synopsys DC compiler)
• Developed a design in RTL to run the bellman-ford algorithm using 3 SRAM’s in Verilog. RTL code was synthesized to
generate a netlist using Synopsys design compiler and passed all timing constraints.
• Different optimizations techniques were used to minimize the delays and to increase the performance.
Twitter Sentiment Analysis (Python, JSON, NLTK)
• Developed and programmed an approach for sentiment analysis, based on computation of semantic orientation score for
positive and negative vocabulary using python.
Simulator for Out-of-order RISC superscalar processor (C++)
• Modelled a C++ functional simulator for MIPS type architecture having nine stage superscalar processor pipeline. Major
emphasis was on dynamic instruction scheduling, issue queues and register renaming. Instructions per cycle (IPC) was used
to conclude the optimal configuration for dynamic scheduling.
Branch Predictor Simulator (C++)
• Constructed a simulator to implement bimodal, gshare and hybrid branch predictors well suited to the SPECint95
benchmarks. Instruction traces were used with actual outcomes to study their effects on misprediction rates.
Cache Hierarchy Design simulator (C)
• Designed a multi-level cache configurable simulator in C. Analyzed the performance using statistics such as miss rate,
memory traffic, and average access time by varying cache size, associativity and block size for LRU, FIFO and LFU with
dynamic aging replacement policies.
Implementation of Multilevel Cache Coherence Protocols (C)
• Modelled a 2 level cache hierarchy of flexible size with write-through, write no-allocate policy, LRU replacement policy
using C and implemented MSI, MESI and dragon protocols in the shared memory multiprocessor system.
Class Portal Management System (Ruby, SQL, Heroku)
• Built a web application for class portal using Ruby on Rails framework with a PostgreSQL database. Some of the
functionalities include grading the student, adding the instructors, managing students activity by admin.
Research Assistant – IIT-Hyderabad (IRIS Recognition with a local database)
• Using C, a Dual IRIS scanner was configured to capture infrared images of the eye.
• Constructed local database for GUI to store all the IRIS images of the users to analyse the recognition and matching
algorithms. Developed GUI interface for an IRIS recognition system in MATLAB to identify and match functions.