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VLSI : An Automotive Applications
Perspective
Navaneethakrishnan Ramanathan, M.E, M.B.A, (Ph.D)
Assistant professor, Dept of ECE, Kumaraguru College of Technology, India.
Regional Mentor – Atal Innovation Mission, Niti Aayog, Government of India.
Chairman – IEEE SSIT, EXECOM Member – IEEE Robotics & Automation Society,
Madras Section, India
Vice Chair – Operations – IEEE SIGHT Global committee
IEEE SSIT Sponsored 5 day online FDP on Research Issues in Advanced VLSI
Presented on 21 Aug 2020
QIS College of Engineering and Technology
Ongole, Andhra Pradesh, India.
Mission of IEEE
IEEE's core purpose is to foster technological innovation and excellence for the
benefit of humanity.
Vision of IEEE
IEEE will be essential to the global technical community and to technical
professionals everywhere, and be universally recognized for the contributions of
technology and of technical professionals in improving global conditions.
Contents
• Evolution of electronics in an automobile
• Functional units & strokes of engine
• DEMS – application
• Safety systems - Application
• ADAS
• E/E Architecture & its challenges
• Current demands & requirements / Trends
• Multi-core
• SoB to SoC design
• Low power design
• EMC
Transportation in ancient times (Road)
World’s first automobile – Motor wagen
Courtesy : https://www.pinterest.com/pin/377317275007649251/
Vintage car
Courtesy : https://www.carwale.com/news/vintage-and-classic-cars-permanently-exempted-from-
ngt-ban/
Mid age cars
Courtesy : https://www.youtube.com/watch?v=i8ijX-amReE
Modern car
Courtesy : http://www.chipsetc.com/computer-chips-inside-the-car.html
Electric car
Courtesy : http://www.chipsetc.com/computer-chips-inside-the-car.html
Parts of Automobile
• Basic structure
Frame, suspension, Axle, Wheel
• Power Unit
Engine (Fuel system, carburettor, ignition, exhaust, cooling)
• Transmission system
Gearbox, clutch, Drive shaft
• Controls
Brake, Steering
• Auxiliaries
Head lamp, Indication lamps
• Super structure
Body
Powertrain
Two stroke / Four stroke engines
• http://www.animatedengines.com/
• Engine capacity
• No of cylinders
• CAMs
• Mechanical – Electronic control
Diesel Engine Management System
• Aurix - Tricore Architecture – TC27x
• Developed by Infineon
• 32 bit single chip MC
• It has 3 cores
• Hardwired
• On chip Debugging
Basic Block Diagram – TC275T
IMT (Intelligent Manual Transmission)
Safety systems
• ABS & EBD
• SRS airbag
• ESP – Electronic Stability Program
• https://www.youtube.com/watch?v=LVz9f5WQhCI
Current trends & Future Mobility
https://www.gsaglobal.org/wp-content/uploads/2019/05/Trends-of-Future-EE-Architectures.pdf
Energy efficiency
Levels of automation
Physical system of an autonomous vehicle
AI & IoT
https://www.gsaglobal.org/wp-content/uploads/2019/05/Trends-of-Future-EE-Architectures.pdf
Automotive E/E architecture – Future trends
Challenges and Bottlenecks
https://www.gsaglobal.org/wp-content/uploads/2019/05/Trends-of-Future-EE-Architectures.pdf
Multicore Architecture
Multicore - Drivers Moore’s law
Moore's law is the observation that the
number of transistors in a dense integrated
circuit (IC) doubles about every two years
As the number of transistors increases, the
number of cores increases accordingly
https://en.wikipedia.org/wiki/Moore%27s_law
https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-172-performance-engineering-of-software-systems-fall-
2018/lecture-slides/MIT6_172F18_lec6.pdf
Multicore - Drivers
Over-clocking in Single cores vs Multicores
Improved Power Consumption as an Incentive for
Multicore (MPC8641) *
*https://www.nxp.com/files-static/32bit/doc/ref_manual/EMBMCRM.pdf
Doubling the frequency causes a fourfold
increase in power consumption
Higher frequencies need increased
voltage because processors with higher
speed transistors leak more than slow
ones
Multicore
Limits to Instruction level Parallelism
Instruction level Parallelism refers to the number of instructions that can be executed in parallel
How to achieve it:
 Compiler level optimization
 Hardware techniques
Limitations are:
 Data dependency
 Procedural dependency
 Resource conflicts
General organization of a 3 way superscalar processor
Pic Source: https://www.oreilly.com/library/view/algorithms-and-parallel/9780470934630/c02-sec1-0007.xhtml
Multicore - Drivers
The act of balancing
Increased
Performance
Reduced Power
and Heat
consumption
Goal is to achieve higher
performance with lower
power consumption
Multicore
SingleCore Vs Multicore – A quick comparison
Parameter Single core processor Multicore processor
Number of cores on a die Single Multiple
Instruction Execution Can execute single thread or task
at a time
Can execute multiple tasks by using
multiple cores
Gain Speed up every program or
software being executed
Speed up the programs which are
designed for multi-core processors
Performance Dependent on the clock
frequency of the core
Dependent on the frequency,
number of cores and program to be
executed
http://www.ecs.umass.edu/ece/andras/courses/ECE668/Mylectures/Introduction_to_Multi_Core.pdf
Multicore Architectures
Types of Multicore
Cores are not identical and
implement different instruction sets
Cores are identical and execute the
same instruction set
*https://www.nxp.com/files-static/32bit/doc/ref_manual/EMBMCRM.pdf
Multicore Architectures
Heterogeneous Multicore Example
Cores that have been optimized for different things are combined to create the best of different worlds
Benefits
Performance optimization
Improved system reliability and security
Low power consumption
NXP’s i.MX7 is a heterogeneous Multicore SoC. It has:
an ARM Cortex-A7 (one or two cores)
o Run an OS like Linux on the Cortex-A7 core
One ARM Cortex-M4 core
o Real-time OS like FreeRTOS on the Cortex-M4
efficient
https://www.witekio.com/blog/introduction-heterogeneous-multicore-processing-architecture/
https://www.embeddedartists.com/heterogeneous-multi-core-processing/
https://blog.nxp.com/tech-insights/3-reasons-why-embedded-heterogeneous-systems-are-more-
Multicore Architectures
Homogeneous Multicore Example
Infineon AURIX Multicore controllers – TC2XX,
TC3XX series
3 cores to 6 cores controllers
Access to the complete memory and peripherals
SPI (Serial Peripheral Interface) crossbar to
connect the cores
Lockstep core – ASIL standard
Communication between Processing elements in Multicore
Multicore communication architecture
Affects scalability of the system
o How many more additional cores/processing elements
can be added?
Affects performance and energy efficiency
o How fast can processors, caches, and memory
communicate?
o Data latency: How long are the latencies to memory?
o How much energy is spent on communication?
Communication Arch. Impacts scalability and performance!
Connection between processing elements, connection between Processing elements and
Memory/Peripherals
Types of communication:
1. Point-To-Point
2. Bus
3. Cross bar
4. NoC (Network-On-Chip)
https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf
Multicore communication architecture
Point-To-Point communication
Point-to-Point Connections
o Every node connected to every other node
o Lowest Latency
o High cost
o Not scalable
o HyperTransport – Used in Nvidia nForce chipsets,
AMD’s Athlon chips
https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf
Multicore communication architecture
Communication between Processing elements in Multicore
Shared bus
o Simple
o Cost effective for a small number of nodes
o Not scalable
o High contention resulting in fast saturation
https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf
Pic source: Real world Multicore embedded systems – Bryon Moyer
Multicore communication architecture
Communication between Processing elements in Multicore
Crossbar
o Every node connected to every other
o Enables concurrent sends to non-conflicting
destinations
o Good for small number of nodes
o Low latency and high throughput
o Not scalable
https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf
Multicore communication architecture
Communication between Processing elements in
Multicore
Network-On-Chip (NoC)
o A NoC is constructed from multiple point-to-
point data links interconnected by switches
(routers), such that messages can be
relayed from any source module to any
destination module over several links, by
making routing decisions at the switches
o Reduces wiring complexity
o Predictable speed
o Reliability
https://sites.google.com/site/alexandrutopirceanu/research/networks-on-chips
`www.ecs.umass.edu/ece/andras/courses/ECE668/Mylectures/Introduction_to_Multi_Core.pdf
Multicore Memory Architecture
Why memory architecture is important for
Multicore?
Memory speeds did not advance as fast as the processing elements
o Consequence: Data access latency: Processor outruns memory, leading to decreased utilization
Symmetric Multi-Processing (SMP)
• Identical memory access latencies for
all processors
• Performance penalty if performance
depends on memory bandwidth
Non-Uniform Memory Access (NUMA)
• Faster access to local memory
• Higher latencies to remote memories
Memory is much slower compared to processing element
Automotive E/E arch and impact on Hardware used
High Complexity Meets Automotive Safety And Reliability
https://www.gsaglobal.org/wp-content/uploads/2019/05/Trends-of-Future-EE-Architectures.pdf
Multicore hardware in Automotive
STMicroelectronics
STMicroElectronics-Brochures
Power Architecturecores
SPC56 B-,C-,D- line – Body andConvenience
applns, Focus: Networking & security
SPC56 P-,L- line – Chassis &Safety
SPC56A-, M- line – Transmission & Timing
relevant applications
42
Multicore hardware in Automotive
NXP’s MAC57D5XX
Arm-based multi-core architectureplatform
o Cortex-A5, 32-bit CPU (application processor)
o Cortex-M4, 32-bit CPU (vehicle processor)
o Cortex-M0+, 32-bit CPU (I/O processor)
Target Application – Instrumentationcluster
NXP also provides microcontrollers (Power
architecture) for other automotive applications like
Powertrain, Chassis etc
NXP also provides SoC with both micro controllers
and microprocessors – Essential for next gen vehicle
controllers
43
RBEI/EES-EC-EP2 | 2020-07-24
NXP Product
Multicore hardware in Automotive
Infineon AURIX series
Target applications: Powertrain domaincontroller,
chassis, Body electronics, Battery management
AURIX series has 3 cores to 6cores
Infineon Tricore architecture
Enhanced Safety and Securityconcepts
Improvednetworking (Ethernet)
SOTA (Software Over the Air) support
44
RBEI/EES-EC-EP2 | 2020-07-24
https://www.infineon.com/dgdl/Infineon-TriCore_Family_BR-ProductBrochure-v01_00-
EN.pdf?fileId=5546d4625d5945ed015dc81f47b436c7
Multicore hardware in Automotive
Renesas controller
Target applications: Body electronics,Chassis
Upto 4 cores (Renesas G4MH cores)
Enhanced Safety and Securityconcepts
Improvednetworking (Ethernet)
SOTA (Software Over the Air) support
Multicore hardware in Automotive
Kilocore: A Manycore chip fromUCDavis
Microchip containing 1,000 independent programmable
processors
Max clock frequency 1.78Ghz
Maximum computation rate of 1.78 trillion instructions per
second
Contains 621 million transistors
Fabricated by IBM using their 32 nm CMOS technology
Independently clocked processors can shutdown
themselves for energy efficiency when not in use
1,000 processors can execute 115 billion instructions per
second while dissipating only 0.7 Watts, low enough to be
powered by a single AA battery
Applications include wireless coding/decoding, video
processing, encryption etc that work on large amounts of
data
46
https://www.ucdavis.edu/news/worlds-first-1000-processor-chip/
Multicore hardware in Automotive
Multicore Vs Manycore
Manycore processors are specialist multicore processors designed for a high degree of parallel
processing:
o Contains numerous simpler, independent cores (from a few tens of cores to thousands or
more)
o Manycore processors are used extensively in High Performance Computing (HPC)
o Optimized for high degree of parallelism, throughput at the expense of single thread
performance
o Software optimized to run in parallel executes more efficiently
https://en.wikipedia.org/wiki/Manycore_processor
SoC Architecture
Embedded system design to SoC Design
SoC Design paradigm
Xilinx – Zynq 7000 – Automotive grade - ADAS
https://www.xilinx.com/products/silicon-devices/soc/xa-zynq-
7000.html#productTable
Low Power design –
Approximate Computing
Approximate computing
• Is 30/8 < 25 ??
• Is 30/8 > 10 ??
• 30/80 = ??
• More accurate -> more energy
consumption, more time
• Different application require
different accuracy in computation
• Error tolerance matters
Approximate computing – Adding third
dimension
Dark silicon
• In the electronics industry, dark silicon is the amount of
circuitry of an integrated circuit that cannot be
powered-on at the nominal operating voltage for a
given thermal design power (TDP) constraint.
• This is a challenge in the era of nanometer
semiconductor nodes, where transistor scaling and
voltage scaling are no longer in line with each other,
resulting in the failure of Dennard scaling.
https://www.researchgate.net/figure/Reduced-on-chip-activity-with-technology-node-scaling-and-dark-silicon-
Semiconductor_fig1_330441344
EMI / EMC
EMI & EMC in Automotive
• Electro Magnetic Interference – Interference by a system, sub system
or component by generating unintended RF energy to another
electronic gadget
*Emissions
• Electro Magnetic Compatibility – Ability of an electronic gadget to
function properly vin EM environment without getting affected or
affecting other systems or subsystems or device.
*Immunity
EMI is complex in automotive environment
Automobile consists of
• Electromechanical
components
• Electronic devices
• Mechanical components
(wiring harness & connectors)
Navaneethakrishnan @ Navin
Email : navaneethakrishnan@ieee.org
Phone : +91 9944147137 (WhatsApp)
Facebook | Linkedin : Navaneethakrishnan Ramanathan

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VLSI- An Automotive Application Perspective

  • 1. VLSI : An Automotive Applications Perspective Navaneethakrishnan Ramanathan, M.E, M.B.A, (Ph.D) Assistant professor, Dept of ECE, Kumaraguru College of Technology, India. Regional Mentor – Atal Innovation Mission, Niti Aayog, Government of India. Chairman – IEEE SSIT, EXECOM Member – IEEE Robotics & Automation Society, Madras Section, India Vice Chair – Operations – IEEE SIGHT Global committee IEEE SSIT Sponsored 5 day online FDP on Research Issues in Advanced VLSI Presented on 21 Aug 2020 QIS College of Engineering and Technology Ongole, Andhra Pradesh, India.
  • 2. Mission of IEEE IEEE's core purpose is to foster technological innovation and excellence for the benefit of humanity. Vision of IEEE IEEE will be essential to the global technical community and to technical professionals everywhere, and be universally recognized for the contributions of technology and of technical professionals in improving global conditions.
  • 3. Contents • Evolution of electronics in an automobile • Functional units & strokes of engine • DEMS – application • Safety systems - Application • ADAS • E/E Architecture & its challenges • Current demands & requirements / Trends • Multi-core • SoB to SoC design • Low power design • EMC
  • 5. World’s first automobile – Motor wagen Courtesy : https://www.pinterest.com/pin/377317275007649251/
  • 6. Vintage car Courtesy : https://www.carwale.com/news/vintage-and-classic-cars-permanently-exempted-from- ngt-ban/
  • 7. Mid age cars Courtesy : https://www.youtube.com/watch?v=i8ijX-amReE
  • 8. Modern car Courtesy : http://www.chipsetc.com/computer-chips-inside-the-car.html
  • 9. Electric car Courtesy : http://www.chipsetc.com/computer-chips-inside-the-car.html
  • 10.
  • 11. Parts of Automobile • Basic structure Frame, suspension, Axle, Wheel • Power Unit Engine (Fuel system, carburettor, ignition, exhaust, cooling) • Transmission system Gearbox, clutch, Drive shaft • Controls Brake, Steering • Auxiliaries Head lamp, Indication lamps • Super structure Body Powertrain
  • 12. Two stroke / Four stroke engines • http://www.animatedengines.com/ • Engine capacity • No of cylinders • CAMs • Mechanical – Electronic control
  • 13. Diesel Engine Management System • Aurix - Tricore Architecture – TC27x • Developed by Infineon • 32 bit single chip MC • It has 3 cores • Hardwired • On chip Debugging
  • 14. Basic Block Diagram – TC275T
  • 15. IMT (Intelligent Manual Transmission)
  • 16. Safety systems • ABS & EBD • SRS airbag • ESP – Electronic Stability Program • https://www.youtube.com/watch?v=LVz9f5WQhCI
  • 17.
  • 18. Current trends & Future Mobility https://www.gsaglobal.org/wp-content/uploads/2019/05/Trends-of-Future-EE-Architectures.pdf
  • 21. Physical system of an autonomous vehicle
  • 24. Automotive E/E architecture – Future trends Challenges and Bottlenecks https://www.gsaglobal.org/wp-content/uploads/2019/05/Trends-of-Future-EE-Architectures.pdf
  • 26. Multicore - Drivers Moore’s law Moore's law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years As the number of transistors increases, the number of cores increases accordingly https://en.wikipedia.org/wiki/Moore%27s_law https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-172-performance-engineering-of-software-systems-fall- 2018/lecture-slides/MIT6_172F18_lec6.pdf
  • 27. Multicore - Drivers Over-clocking in Single cores vs Multicores Improved Power Consumption as an Incentive for Multicore (MPC8641) * *https://www.nxp.com/files-static/32bit/doc/ref_manual/EMBMCRM.pdf Doubling the frequency causes a fourfold increase in power consumption Higher frequencies need increased voltage because processors with higher speed transistors leak more than slow ones
  • 28. Multicore Limits to Instruction level Parallelism Instruction level Parallelism refers to the number of instructions that can be executed in parallel How to achieve it:  Compiler level optimization  Hardware techniques Limitations are:  Data dependency  Procedural dependency  Resource conflicts General organization of a 3 way superscalar processor Pic Source: https://www.oreilly.com/library/view/algorithms-and-parallel/9780470934630/c02-sec1-0007.xhtml
  • 29. Multicore - Drivers The act of balancing Increased Performance Reduced Power and Heat consumption Goal is to achieve higher performance with lower power consumption
  • 30. Multicore SingleCore Vs Multicore – A quick comparison Parameter Single core processor Multicore processor Number of cores on a die Single Multiple Instruction Execution Can execute single thread or task at a time Can execute multiple tasks by using multiple cores Gain Speed up every program or software being executed Speed up the programs which are designed for multi-core processors Performance Dependent on the clock frequency of the core Dependent on the frequency, number of cores and program to be executed http://www.ecs.umass.edu/ece/andras/courses/ECE668/Mylectures/Introduction_to_Multi_Core.pdf
  • 31. Multicore Architectures Types of Multicore Cores are not identical and implement different instruction sets Cores are identical and execute the same instruction set *https://www.nxp.com/files-static/32bit/doc/ref_manual/EMBMCRM.pdf
  • 32. Multicore Architectures Heterogeneous Multicore Example Cores that have been optimized for different things are combined to create the best of different worlds Benefits Performance optimization Improved system reliability and security Low power consumption NXP’s i.MX7 is a heterogeneous Multicore SoC. It has: an ARM Cortex-A7 (one or two cores) o Run an OS like Linux on the Cortex-A7 core One ARM Cortex-M4 core o Real-time OS like FreeRTOS on the Cortex-M4 efficient https://www.witekio.com/blog/introduction-heterogeneous-multicore-processing-architecture/ https://www.embeddedartists.com/heterogeneous-multi-core-processing/ https://blog.nxp.com/tech-insights/3-reasons-why-embedded-heterogeneous-systems-are-more-
  • 33. Multicore Architectures Homogeneous Multicore Example Infineon AURIX Multicore controllers – TC2XX, TC3XX series 3 cores to 6 cores controllers Access to the complete memory and peripherals SPI (Serial Peripheral Interface) crossbar to connect the cores
  • 34. Lockstep core – ASIL standard
  • 35. Communication between Processing elements in Multicore Multicore communication architecture Affects scalability of the system o How many more additional cores/processing elements can be added? Affects performance and energy efficiency o How fast can processors, caches, and memory communicate? o Data latency: How long are the latencies to memory? o How much energy is spent on communication? Communication Arch. Impacts scalability and performance! Connection between processing elements, connection between Processing elements and Memory/Peripherals Types of communication: 1. Point-To-Point 2. Bus 3. Cross bar 4. NoC (Network-On-Chip) https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf
  • 36. Multicore communication architecture Point-To-Point communication Point-to-Point Connections o Every node connected to every other node o Lowest Latency o High cost o Not scalable o HyperTransport – Used in Nvidia nForce chipsets, AMD’s Athlon chips https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf
  • 37. Multicore communication architecture Communication between Processing elements in Multicore Shared bus o Simple o Cost effective for a small number of nodes o Not scalable o High contention resulting in fast saturation https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf Pic source: Real world Multicore embedded systems – Bryon Moyer
  • 38. Multicore communication architecture Communication between Processing elements in Multicore Crossbar o Every node connected to every other o Enables concurrent sends to non-conflicting destinations o Good for small number of nodes o Low latency and high throughput o Not scalable https://www.cs.umd.edu/class/spring2015/cmsc411-0201/lectures/lecture22-interconnects.pdf
  • 39. Multicore communication architecture Communication between Processing elements in Multicore Network-On-Chip (NoC) o A NoC is constructed from multiple point-to- point data links interconnected by switches (routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches o Reduces wiring complexity o Predictable speed o Reliability https://sites.google.com/site/alexandrutopirceanu/research/networks-on-chips `www.ecs.umass.edu/ece/andras/courses/ECE668/Mylectures/Introduction_to_Multi_Core.pdf
  • 40. Multicore Memory Architecture Why memory architecture is important for Multicore? Memory speeds did not advance as fast as the processing elements o Consequence: Data access latency: Processor outruns memory, leading to decreased utilization Symmetric Multi-Processing (SMP) • Identical memory access latencies for all processors • Performance penalty if performance depends on memory bandwidth Non-Uniform Memory Access (NUMA) • Faster access to local memory • Higher latencies to remote memories Memory is much slower compared to processing element
  • 41. Automotive E/E arch and impact on Hardware used High Complexity Meets Automotive Safety And Reliability https://www.gsaglobal.org/wp-content/uploads/2019/05/Trends-of-Future-EE-Architectures.pdf
  • 42. Multicore hardware in Automotive STMicroelectronics STMicroElectronics-Brochures Power Architecturecores SPC56 B-,C-,D- line – Body andConvenience applns, Focus: Networking & security SPC56 P-,L- line – Chassis &Safety SPC56A-, M- line – Transmission & Timing relevant applications 42
  • 43. Multicore hardware in Automotive NXP’s MAC57D5XX Arm-based multi-core architectureplatform o Cortex-A5, 32-bit CPU (application processor) o Cortex-M4, 32-bit CPU (vehicle processor) o Cortex-M0+, 32-bit CPU (I/O processor) Target Application – Instrumentationcluster NXP also provides microcontrollers (Power architecture) for other automotive applications like Powertrain, Chassis etc NXP also provides SoC with both micro controllers and microprocessors – Essential for next gen vehicle controllers 43 RBEI/EES-EC-EP2 | 2020-07-24 NXP Product
  • 44. Multicore hardware in Automotive Infineon AURIX series Target applications: Powertrain domaincontroller, chassis, Body electronics, Battery management AURIX series has 3 cores to 6cores Infineon Tricore architecture Enhanced Safety and Securityconcepts Improvednetworking (Ethernet) SOTA (Software Over the Air) support 44 RBEI/EES-EC-EP2 | 2020-07-24 https://www.infineon.com/dgdl/Infineon-TriCore_Family_BR-ProductBrochure-v01_00- EN.pdf?fileId=5546d4625d5945ed015dc81f47b436c7
  • 45. Multicore hardware in Automotive Renesas controller Target applications: Body electronics,Chassis Upto 4 cores (Renesas G4MH cores) Enhanced Safety and Securityconcepts Improvednetworking (Ethernet) SOTA (Software Over the Air) support
  • 46. Multicore hardware in Automotive Kilocore: A Manycore chip fromUCDavis Microchip containing 1,000 independent programmable processors Max clock frequency 1.78Ghz Maximum computation rate of 1.78 trillion instructions per second Contains 621 million transistors Fabricated by IBM using their 32 nm CMOS technology Independently clocked processors can shutdown themselves for energy efficiency when not in use 1,000 processors can execute 115 billion instructions per second while dissipating only 0.7 Watts, low enough to be powered by a single AA battery Applications include wireless coding/decoding, video processing, encryption etc that work on large amounts of data 46 https://www.ucdavis.edu/news/worlds-first-1000-processor-chip/
  • 47. Multicore hardware in Automotive Multicore Vs Manycore Manycore processors are specialist multicore processors designed for a high degree of parallel processing: o Contains numerous simpler, independent cores (from a few tens of cores to thousands or more) o Manycore processors are used extensively in High Performance Computing (HPC) o Optimized for high degree of parallelism, throughput at the expense of single thread performance o Software optimized to run in parallel executes more efficiently https://en.wikipedia.org/wiki/Manycore_processor
  • 49. Embedded system design to SoC Design
  • 51. Xilinx – Zynq 7000 – Automotive grade - ADAS https://www.xilinx.com/products/silicon-devices/soc/xa-zynq- 7000.html#productTable
  • 52. Low Power design – Approximate Computing
  • 53. Approximate computing • Is 30/8 < 25 ?? • Is 30/8 > 10 ?? • 30/80 = ?? • More accurate -> more energy consumption, more time • Different application require different accuracy in computation • Error tolerance matters
  • 54. Approximate computing – Adding third dimension
  • 55. Dark silicon • In the electronics industry, dark silicon is the amount of circuitry of an integrated circuit that cannot be powered-on at the nominal operating voltage for a given thermal design power (TDP) constraint. • This is a challenge in the era of nanometer semiconductor nodes, where transistor scaling and voltage scaling are no longer in line with each other, resulting in the failure of Dennard scaling. https://www.researchgate.net/figure/Reduced-on-chip-activity-with-technology-node-scaling-and-dark-silicon- Semiconductor_fig1_330441344
  • 57. EMI & EMC in Automotive • Electro Magnetic Interference – Interference by a system, sub system or component by generating unintended RF energy to another electronic gadget *Emissions • Electro Magnetic Compatibility – Ability of an electronic gadget to function properly vin EM environment without getting affected or affecting other systems or subsystems or device. *Immunity
  • 58. EMI is complex in automotive environment Automobile consists of • Electromechanical components • Electronic devices • Mechanical components (wiring harness & connectors)
  • 59.
  • 60. Navaneethakrishnan @ Navin Email : navaneethakrishnan@ieee.org Phone : +91 9944147137 (WhatsApp) Facebook | Linkedin : Navaneethakrishnan Ramanathan