Comparative Evaluation of Three Phase Three Level Neutral Point Clamped Z-Source Inverters using Advanced PWM Control Strategies

International Journal of Electronic and Electrical Engineering.
ISSN 0974-2174 Volume 5, Number 3 (2012), pp. 239-254
© International Research Publication House
http://www.irphouse.com
Comparative Evaluation of Three Phase Three Level
Neutral Point Clamped Z-Source Inverters using
Advanced PWM Control Strategies
K. Sreekanth, S. Nagaraja Rao and D.V. Ashok Kumar
Dept. of EEE, SDIT, Nandyal,
sreekanth266@gmail.com
Dept. of EEE, RGMCET, Nandyal
nagarajraomtech@gmail.com
Dept. of EEE, SDIT, Nandyal
principal.sdit@gmail.com
Abstract
Three-level Z-source inverters are recent single-stage topological solutions
proposed for buck-boost energy conversion with all favorable advantages of
three-level switching retained. Despite their effectiveness in achieving voltage
buck-boost conversion, existing three-level Z-source inverters use two
impedance networks and two isolated dc sources, which can significantly
increase the overall system cost and require a more complex modulator for
balancing the network inductive voltage boosting. Offering a number of less
costly alternatives, this paper presents the design and control of two three-
level Z-source inverters, whose output voltage can be stepped down or up
using only a single impedance network connected between the dc input source
and either a neutral-point-clamped (NPC) or dc-link cascaded inverter
circuitry.
This paper investigates the carrier based modulation schemes (SPWM and
Modified SVPWM) of three-level three phase Z-source inverters with either
two Z-source networks or single Z-source network connected between the dc
sources and inverter circuitry. With the proper offset added for achieving both
optimized harmonic performance and fundamental output voltage, the
proposed modulation schemes of three-level Z-source inverters can satisfy the
expected boost operation under unbalanced modulation conditions. The
Simulation has been performed through Matlab/Simulink and relative
simulation results with conventional method have been presented to validate
the proposed method.

240 K. Sreekanth et al
Index Terms — Neutral-point clamped (NPC) Z-source inverters, PWM
Schemes, THD.
INTRODUCTION
The Z-impedance network consists of L and C components connected in an X fashion.
The firing control of the Z-source inverter includes the shoot through states. The Z-
source inverter advantageously utilizes the shoot-through state to boost the DC bus
voltage by gating on both the upper and lower switches of a phase leg. Three-level
neutral-point-clamped (NPC) inverters, having many inherent advantages, are
commonly used as the preferred topology for medium voltage ac drives [1], and have
recently been explored for other low-voltage applications including grid-interfacing
power converters and high-speed drive converters [2], [3]. Despite their generally
favorable output performance, NPC inverters are constrained by their ability to
perform only voltage-buck operation with buck-boost energy conversion, usually
achieved by connecting various dc-dc boost converters to the front ends of the dc-ac
inverters. These two-stage solutions are usually more costly and can be harder to
control, since they involve more active and passive components. Offering a single-
stage solution, [4], [5] propose the buck-boost Z-source NPC inverter, whose
topology is illustrated in Fig. 1 (can be viewed as an extension from the two-level Z-
source inverter proposed in [6]). Compared to the traditional NPC inverter, the
inverter in Fig. 1 uses two additional Z-source impedance networks for boosting its dc
input voltage from Vdc to a higher dc link voltage for driving the inverter directly.
Although theoretically feasible, the inverter in Fig. 1 is not a favorable economical
solution, since it uses two isolated dc sources and a number of passive elements,
which can significantly increase the cost, size and weight of the inverter.
Fig.1 Topology of Z-source NPC inverter with two LC impedance networks.
With the above-described disadvantages in view and aiming to offer better
alternatives, this letter presents the design of a Z-source NPC inverter that use only
half the passive elements. With the integration of an appropriate pulse-width

Comparative Evaluation of Three Phase Three Level Neutral Point 241
modulation (PWM) scheme, the proposed inverters can operate with the correct volt-
sec average and inductive voltage boosting produced at all instances, while using only
the minimum of six device commutations per switching cycle for continuous PWM
switching. Therefore, compared to the dual Z-source NPC inverter presented in [4],
[5], the single Z-source inverters proposed in this letter have equally good
Performance with only a slight degradation in high-frequency switching (not
fundamental) performance expected. This is more than compensated by the reduced
element count and lower system cost achieved by the inverters. Implementation wise,
the inverters can be controlled using a generic alternative phase opposition disposition
(APOD) carrier-based modulator with an appropriate triplen offset and time
advance/delay added.
OPERATIONAL PRINCIPLES OF SINGLE Z- SOURCE THREE-
LEVEL INVERTERS
Fig. 2 shows the topologies of the proposed Z- source NPC and DCLC inverters,
where a single Z-source impedance network, consisting of a split inductor (L1 and L2)
and two capacitors (C1 and C2) are connected between the input split-dc source (can
be implemented using a single dc source and two series-connected capacitors) and
inverter circuitry. Compared to the inverter topology shown in Fig. 1, the proposed Z-
source inverters clearly have the advantage of using only half the passive components
and only a single split-dc source, which can either be isolated or non-isolated.
Although the system cost is not expected to drop by half, since the voltage rating of
the dc capacitors needed by the proposed inverter is nearly double that of the inverter
shown in Fig. 1 (current rating of the inductors remains unchanged), the saving is still
expected to be relatively sizable. This is because the proposed inverters use only a
single split-dc source, implying that isolation transformers and additional rectifier
circuits needed by the inverter in Fig. 1 (if isolated dc power supplies are not readily
available) are omitted.
Fig.2: Topology of Z-source NPC inverter using only a single LC impedance
networks.

Under voltage-buck operation, the Z-source inverters are controlled with their ac
outputs transiting between the three distinct voltage levels of 0 V and using the phase-
leg switching states shown in Table I, which in principle are similar to those assumed
by a traditional three-level inverter. Alternatively, when voltage-boost operation is
commanded, both inverters must function with an additional shoot-through state
inserted. A visibly obvious method for introducing the shoot-through state is to turn
ON all switches from the same phase-leg simultaneously (e.g., {SA1, SA1
1, SA2,
SA1
2} in Fig.2) to give the simplified circuit representation shown in Fig. 3(a) with
input diodes D1 and D2 open-circuited. (Note that the turning ON of all switches
from a phase leg to effect a short circuit is not the “minimal-loss” method, as
explained in Section III, where a better shoot-through technique is also presented.) It
is inferred that the presented Z-source inverters do not need dead-time delay for short-
circuit protection, unlike most traditional inverters. Thus, the presented Z-source
inverters are expected to perform better, since performance limitations commonly
associated with dead-time delay are avoided.
Fig. 3. Simplified representations of single Z-source inverters when in (a) shoot-
through and (b) non-shoot-through states.
Table 1. Switching states of Three level Z-Source NPC
State Type ON Switches ON Diodes
Non Shoot-through SA1,SA2 D1,D2 +
2
Non Shoot-through SA2, 1 D1,D2
DA1orDA2 0
NonShoot- through 1, 2 D1,D2 −
2

Shoot- through
(not preferred)
SA1,SA2,
1, 2 . . . .. . 0
Shoot-through
(preferred)
SA1,SA2,
1,SB2, 1, 2
DA2,DB1
0
Using the simplified circuit shown in Fig. 3(a) and assuming that VL1 = VL2 = VL
and VC1 = VC2 = VC for a symmetrical network, the capacitive and inductive voltages
of the single Z-source impedance network can be expressed as (1) during the shoot-
through durationT0.
VL = VC ------------- (1)
Upon reverting to a non-shoot-through state during interval T1, the inverters
resume the circuit representation shown in Fig. 3(b), where the inverter circuitry and
external load are represented by a simplified current source. Using this circuit
representation, the capacitive and inductive voltages are re-expressed as
VL = 2Vdc – VC
Averaging VL over a switching cycle T then gives
VC = 2 Vdc (1-T0/T)/(1-2 T0/T) ------ (2)
Using (2), the inverter dc-link voltage Vi and peak ac output voltage Vx ( x =A,B
or C ) when in a non-shoot-through state are derived as
Vi = VC - VL = 2 VC – 2 Vdc = 2 Vdc/(1-2 T0/T)
Vx = M Vi /2 = M B Vdc
where M is modulation index and B is is the boost factor (B = 1/(1-2 T0/T)) , which
should be set to unity for voltage-buck operation and B > 1 for voltage-boost
operation.
MODULATION SCHEME FOR TWO LEVEL ZSI
Being different from the balanced three-phase operation, the carrier-based references
have to be generated using appropriate offset plus the primarily derived sine waves.
For optimizing the harmonic performance, the expected offset in sine-triangle
modulation has been induced in [11] which would be summarized here briefly to
demonstrate the three phase operation clearly. The offset for two-level optimal
switching can be mathematically expressed as:
V =
−V 2
⁄ , V > 0
−V 2
⁄ , V < 0
−(V + V ) 2
⁄ , V > 0 V < 0
Where, Vmax = max(Va, Vb Vc) and Vmin = min(Va, Vb Vc). The offset for
multilevel optimal switching therefore can be further derived from

Where
For a three-phase-leg two level VSI, both continuous switching (e.g., centered
SVM) and discontinuous switching (e.g., 60 – discontinuous PWM) are possible with
each having its own unique null placement at the start and end of a switching cycle
and characteristic harmonic spectrum. The same strategies with proper insertion of
shoot through modes could be applied to the three-phase-leg Z–source inverter with
each having the same characteristic spectrum as its conventional counterpart [3].
There are fifteen switching states of a three-phase-leg z-source inverter.
Fig.4. Traditional switching pattern for 2-level Z-Source inverter
Fig.5. Modified switching pattern of Z-Source inverter

To easily achieve this kind of shoot-through insertion for the whole fundamental
period, the references can then be expressed as:
Where /T = shoot through duty ratio.
Where, X = A, B or C
MODULATION SCHEMES FOR THREE LEVEL ZSI
4.1 Modulation Development for Three Level Z Source Inverter:
In the proposed work of carrier-based implementation, the phase disposition PWM
scheme is used. The rules for the phase disposition method, when the number of level
m = 3, are
 The (m –1) = 2 carrier waveforms are arranged so that every carrier is in phase.
 The converter is switched to + Vdc when the reference is greater than both carrier
waveforms.
 The converter is switched to zero when the reference is greater than the lower carrier
waveform but less than the upper carrier waveform. The converter is switched to - Vdc
when the reference is less than both carrier waveforms.
 In the carrier-based implementation at every instant of time the modulation signals are
compared with the carrier and depending on which is greater, the definition of the
switching pulses is generated.
Fig. 6 .Modulation of Traditional and ZSI of Three level

Fig.7: Pulse generation of Three Level ZSI using Sinusoidal Pulse Width Modulation.
4.2 Modified Reference Modulated Technique (SVPWM):
In the SPWM scheme for three-level inverters, each reference phase voltage is
compared with the triangular carrier and the individual pole voltages are generated,
independent of each other. To obtain the maximum possible peak amplitude of the
fundamental phase voltage, in linear modulation, a common mode voltage, Voffset1,
is added to the reference phase voltages, where the magnitude of Voffset1 is given by
2
)
( min
max
1
V
V
Voffset


 --------- (4.1)
4.2.1 Modified Reference with triangular carrier modulated technique for three
level Inverters:
In the proposed work, in the carrier-based implementation the phase disposition PWM
scheme is used. For 3-level ZSI (m –1) = 2 carrier waveforms are arranged so that
every carrier is in phase. In the carrier-based implementation at every instant of time
the modulation signals are compared with the carrier and depending on which is
greater, the definition of the switching pulses is generated.
Fig.8: Pulse generation of Three Level ZSI using Modified Space vector Pulse Width
Modulation.

V. SIMULATION RESULTS
The 3- phase two level and three level Z source inverter configurations are simulated
using MATLAB-SIMULINK tool box. The parameters used for z source inverter are
given in the appendix. Different parameters which are considered for input voltage,
voltage across capacitor, Inverter gain output voltage, line voltage and harmonic
spectra etc…
5.1. Simulation Results for 3-phase Three level Z Source Inverter using dual
impedance networks
5.1.1. Non Shoot-Through State for Three Level ZSI using SPWM at K=0
Fig.9.InputVoltage (Vdc)
Fig.10. Voltage across Capacitor
Fig.11.Inverter Gain Output Voltage
Fig.12. Line Voltage of 3-level ZSI
Fig.13. Line voltage THD

5.1.2. Non Shoot-Through State for Three Level ZSI using modified SVPWM at
k=0
Fig.16. Line Voltage for 3-level ZSI
5.1.3 Shoot-Through State for Three Level SPWM at K=0.2

Fig.20. Line Voltage of Three level ZSI
5.1.4. Shoot-Through State for Three Level Modified SVPWM at K=0.2
Fig.24. Line Voltage

Fig.25.Line voltage THD
5.2. Simulation Results for 3-phase Three level Z Source Inverter using single
impedance network
5.2.1. Non Shoot-Through State for Three Level ZSI using SPWM At K=0
Fig.26.InputVoltage
Fig.29. Line Voltage of 3-level ZSI

5.2.4. Non Shoot-Through State for Three Level Modified SVPWM at k=0
Fig.31.Voltage across Capacitor
Fig.33. Line Voltage for 3-level ZSI
5.2.5. Shoot-Through State for Three Level SPWM at K=0.2

5.2.6. Shoot-Through State for Three Level Modified SVPWM at K=0.2
Fig.40. Inverter Gain Output Voltage
Fig.42.Line voltage THD

VI. Comparison of THD for different PWM techniques of 3-phase 3-
level Z source inverter using dual and single impedance networks
Table 2. Simulation parameters
Parameters Specifications unit
DC supply 200 V
Modulation Index 0.866 -
Output Frequency 50 Hz
Switching Frequency 1000 Hz
Shoot through 0.2 -
= = 1000 µF
= = 1 mH
Load(Resistance) 10 Ώ
Table.3 comparison of results for 3-level ZSI using dual impedance networks
Switching state SPWM Modified
SVPWM
Boost
factor
Fundamental
output
voltage
%
THD
Fundamental
output voltage
%
THD
Non Shoot-through (K=0)
Vi=60V,
V0=60V
49.78 45.51 51.63 44.23 1
Shoot-through
(K=0.2)
Vi=60V,
V0=100V
80.44 36.86 83.12 32.00 1.67
Table.4 comparison of results for 3-level ZSI using single impedance networks
Switching state SPWM Modified
SVPWM
Boost
factor
Fundamental
output
voltage
%
THD
Fundamental
output voltage
%
THD
Non Shoot-through (K=0)
Vi=60V,
V0=60V
53.25 42.65 55.02 37.27 1
Shoot-through
(K=0.2)
Vi=60V,
V0=100V
84.96 37.23 88.3 28.33 1.67

The summary of THD and fundamental output voltage for various Z Source
inverter topologies with their control strategies are presented. i.e., 3-Level Z source
inverter with dual impedance networks and single impedance networks were
simulated using SPWM and modified SVPWM with triangular carriers and it is
concluded that 3-level z source inverter using single impedance network has given
good fundamental output voltage(88.3V) with less THD (28.33%).
Note: By increasing the Switching Frequency THD will decreases. Generally
Switching Frequency is chosen in this paper is 1 kHz but by using high switching
frequency we will get the THD <5%.
VII. CONCLUSION
This paper presents the design of a Z-source NPC inverter that uses only half the
passive elements. With the integration of an appropriate pulse-width modulation
(PWM) scheme, the proposed inverters can operate with the correct volt-sec average
and inductive voltage boosting produced at all instances, while using only the
minimum of six device commutations per switching cycle for continuous PWM
switching. Therefore, compared to the dual Z-source NPC inverter the proposed
single Z-source inverter have equally good performance with good quality of output
voltage and less THD. This is more than compensated by the reduced element count
and lower system cost achieved by the inverters.
REFERENCES
[1] Fang Zheng Peng Alan Joseph ,in Wang , Lihwa Chen Zhiguo Pan ,“ Z-Source
inverter for motor drives” IEEE Trans. On Power Electronics Vol.20.No.4
July,2005.
[2] F.Z.Peng, “ Z-Source inverter”, IEEE Trans. Ind.
Applicat.Mag.,vol.39,no.2,pp.504-510, Mar/Apr.2003.
[3] Yu Tang, Shaojun Xie, Member , IEEE , Chaohua Zhang, And Zegang Xu, “
Improved Z- Source Inverter With Reduced Z-Source Capacitor Voltage Stress
and Soft-Start Capability”,IEEE Trans. On Power Electronics ,vol.24,No.2,Feb
2009.
[4] F.Z.Peng, X.Yuan, X.Fang, and Z.Qian, “ Z-Source /Inverter for adjustable
speed drives”, IEEE Power Electron, Lett, vol.1, no.2, pp.33-35, jun.2004.
[5] Y.Kim and S.Sul,” A Novel ride through system for adjustable speed drives
using common-mode voltage”, IEEE Trans. Ind. Applicat., vol.37, no.5,
pp.1373-1382, sep/oct. 2001.
[6] A. Van Zyl, R. Spec, A. FAveluke, and S.Bhowmik,” Voltage sag ride through
for adjustable speed drives with active receivers”, IEEE Trans. Ind. Applicat,
vol.34 , no.6, pp.1270-1277,Nov/Dec,1998.
[7] Fang Zheng Peng , Miaosen Shen, Zhaoming Qian “ Maximum Boost control
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Comparative Evaluation of Three Phase Three Level Neutral Point Clamped Z-Source Inverters using Advanced PWM Control Strategies

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