3. 3
Moore’s Law (1965-2023):
In 1965, Gordon Moore (Fairchild) stated that
the number of transistors on an IC would
double every year. 10 years later, he revised
his statement, asserting that they double
every 18 months. Since then, this “rule” has
been famously known as Moore’s Law.
4. VLSI DESIGN FLOW
In VLSI, physical design (is also known as
integrated circuit layout) is a process in which the
front-end design transfer the structural netlist to
the back-end design team to convert into a
physical layout database which consists of
geometrical design information for all the physical
layers which is used for interconnections.
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8. LAYOUT LAYERS AND DESIGN
RULES
In a design after the post route stage, There is a
verification checks that’s mandatory in order to process
chip to move into tape-in stage, This verification is
referred as Physical Verification. The physical verification
must be verified during floorplan, placement, STA and
finally after post route stage of design layout.
DRC checks and LVS checks :
To determine if the layout satisfies a set of rules required
for manufacturing. Design rule checks are nothing but
physical checks of metal width, pitch and spacing
requirement for the different layers which depend on
different technology nodes.
Metal DRC, Via DRC, Base DRC
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11. AREAS OF FOCUS
Front end :
RTL verification and design
Design for Testability (DFT)
Analog design engineer
Synthesis and Implementation
Back end :
Physical Design (PD)
Design for Testability (DFT)
Placement and routing (PNR)
Static Timing Analysis (STA)
Physical verification (PV) / Layout Verification (LV)
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