BE-EEE-8th sem project report for the project titled "Asymmetrical Multilevel Inverter for Higher output Voltage Levels”

Asymmetrical Multilevel Inverter for Higher output Voltage Levels” 2015-16
Department of EEE, GCE, Ramanagaram Page 1
Chapter 1
INTRODUCTION
1.1 Foreword
Multilevel inverters with a large number of steps can generate high quality voltage
waveforms, good enough to be considered as suitable voltage source generators. A modified
Sinusoidal Pulse Width Modulation (SPWM) modulator with phase disposition that increases
output waveform up to 7-level while reducing output harmonics is presented in this paper. The
proposed modulation technique can easily be applied to any multilevel inverter topology carrying
out the necessary calculations
Multilevel inverters produce a stepped output phase voltage with a refined harmonic profile when
compared to a two-level inverter [1, 2]. The concept of multilevel inverters, introduced about 30
years ago [1], entails performing power conversion in multiple voltage steps to obtain improved
power quality, lower switching losses, better electromagnetic compatibility, and higher voltage
capability. Nowadays, there exist three commercial topologies of multilevel voltage source
inverters: the most popular being the diode-clamped [3, 4], flying capacitor [5, 6] and cascaded H-
bridge [7-9] structures. Among these inverter topologies, cascaded multilevel inverter reaches the
higher output voltage and power levels, and the higher reliability due to its modular topology and
the simplicity [10].
Among these inverter topologies, the cascaded H-bridge multilevel inverters require the least
number of total main components. One aspect which sets the cascaded H-bridge apart from other
multilevel inverters is the capability of utilizing different DC voltages on the individual H-bridge
cells which results in splitting the power conversion and asymmetrical multilevel inverters can be
obtained [8, 9]. To provide a large number of output steps without increasing the number of DC
voltage sources, asymmetric multilevel converters can be used. The cascaded H-bridge can operate
as symmetric or asymmetric converter. In asymmetric multilevel converters the DC voltage sources
are proposed to be chosen as different value according to different methods [11-13]. Recently,
several multilevel inverter topologies have been developed for cascaded multilevel inverters. Novel
topologies of cascaded multilevel inverters using a reduced number of switches and gate driver
circuits are presented in recent years [14-18]. In [14, 15] novel configuration of cascaded multilevel
inverters have been proposed. The suggested topologies need fewer switches and gate driver circuits

but they require multiple DC sources and some switches of suggested topologies have high peak
inverse voltage
Multilevel Inverter (MLI) offers a number of advantages when compared to the conventional two
level inverter in terms of improved d.c. link utilization and harmonic spectrum. The stepped
approximation of the sinusoidal output waveform with higher levels reduces the harmonic distortion
of the output waveform and the stresses across the semiconductor devices and also allows higher
voltage/current and power ratings. The reduced switching frequency of each individual switch of
the inverter also reduces the switching losses and improves the efficiency of the inverter. The
different types of MLI are diode clamped, flying capacitor, cascaded MLI. Diode clamped requires
more no of diodes and flying capacitor has capacitor balancing problem The cascaded H-bridge
inverters having more no of advantages such as modular structure compare to other topologies such
as modular structure and less no of components it is one of the topologies proposed for drive
applications which meet the requirements such as high power rating with reduced THD and
switching losses. The asymmetric MLI reduces the number of input DC sources required and
increases the number of levels in the output. The modulation strategy used for reducing the THD is
the level shifted carrier based PWM technique and the carriers used are the triangular waves with
same amplitude and frequency. This device has the high power rating, less switching losses, less
conduction loss and it has the ability to with stand high switching stresses in the series connection
employed in this inverter design.. This method proves that the THD in the seven level output can be
highly reduced by CLSPWM technique and most importantly the performance characteristics of the
motor load can be improved by implementing the proposed idea.
Asymmetric multilevel have the same topology as symmetric multilevel inverters. They differ only
in the rating of input dc voltages and control strategies. For many applications it is difficult to use
separate dc sources and too many dc sources will require many long cables and could lead to
voltage imbalance among the dc sources. To reduce the number of dc sources required for the
cascaded H-bridge multilevel inverter, a scheme is proposed which uses lesser number of bridges.
This scheme therefore provides the capability to produce higher voltages at higher speeds with low
switching frequency which has inherent low switching losses and high converter efficiency. A
seven-level asymmetric cascaded Hbridge multilevel inverter has two H-bridges for each phase.

1.2 BASICS--- Full-bridge or “H-bridge” Voltage Source Inverter
Fig-1.2(1) A H BRIDGE CEL
Multilevel inverters have received added awareness for their ability on high-power and
medium voltage function and because of former compensation such as high power quality, lower
order harmonics, mlTIlmUm switching losses and improved electromagnetic interference [4], [5].
And also multilevel inverters are promising; they have virtually sinusoidal output-voltage
waveforms, Output current with improved harmonic profile, a lesser amount of stressing of
electronic components owing to decreased voltages, switching losses that are inferior than those of
predictable two-level inverters, a slighter filter size, and worse EMI, all of which make them
cheaper, lighter, and more compact. Multilevel inverters make small Common mode voltage;
consequently the stress in the bearings of a motor allied to a multilevel motor drive can be
condensed. In addition CM voltages can be eliminated by using advanced modulation technique.
Multilevel inverters can draw input current with low distortion. These inverters can operate at
equally fundamental frequency and high switching frequency PWM. It should be noted that lower
switching frequency means lower switching loss and higher efficiency. These inverters make a
stepped voltage waveform by means of a number of dc voltage sources as the input and a suitable
arrangement of the power-semi conductor-based devices [6]. Three major structures of the
multilevel inverters have been presented: "diode clamped multilevel inverter," "flying capacitor
multilevel inverter," and "cascaded multilevel inverter" [7]. The cascaded multilevel inverter is
collected of a number of single-phase H-bridge inverters and is classified into symmetric and
asymmetric groups based on the magnitude of dc voltage sources. In the symmetric types, all the dc
voltage sources of cascaded H-bridges are having equal magnitudes, whereas in the asymmetric
types, the values of the dc voltage sources of all Hbridges are dissimilar. In topical years, a number
of topologies with various control techniques have been presented for cascaded multilevel inverters

[8]-[9]. In [7] and, diverse symmetric cascaded multilevel inverters have been presented. The
foremost advantage of all these structures is the short variety of dc voltage sources, which is one of
the most significant features in determining the cost of the inverter. On the other hand, because
some of them utilize an elevated number of bidirectional power switches, a high number of
insulated gate bipolar transistors (IGBTs) are necessary, which is the major drawback of these
topologies. Consequently, it increases control complexity, circuit size and cost. The major
advantage of this asymmetric topology and its algorithms is associated to its ability to create a
substantial number of output voltage levels by using a low
number of dc voltage sources and power switches but the high diversity in the magnitude of dc
voltage sources is their most outstanding disadvantage. Recently, asymmetrical and hybrid
multistage topologies are becoming one of the most fascinated research area. In the asymmetrical
configurations, the magnitudes of dc voltage supplies are uneven. These topologies diminish the
cost and size of the inverter and get better reliability since lesser number of power electronic
components, capacitors, and dc supplies are used. The hybrid multistage converters consist of
dissimilar multilevel configurations with uneven dc voltage supplies. Bidirectional switches with an
suitable control technique can enhance the performance of multilevel inverters in terms of falling
the number of semiconductor components, minimizing the withstanding voltage and achieving the
required output voltage with higher levels [10]-[11]. The magnitudes of the utilized dc voltage
supplies have been selected in a way that brings the elevated number of voltage levels with an
effective application of a fundamental frequency staircase modulation technique. For a single-phase
seven-level inverter, 12 power electronic switches are required in both the diode-clamped and the
flying-capacitor topologies.
Asymmetric voltage technology is used in the cascade H-bridge multilevel inverter to allow more
levels of output voltage [12], so the cascade Hbridge multilevel inverter is suitable for applications
with increased voltage levels. Two Hbridge inverters with a dc bus voltage of multiple relationships
can be connected in cascade to produce a single phase seven-level inverter* and eight power
electronic switches are used. In this paper a new asymmetric Bi-directional converter topology
which uses contradictory ratios of dc voltage sources.

Chapter : 2
LITERATURE SURVEY
 Santiago-Gonzalez, 1. Cruz-Colon, R. otero-De-leon, V. lopezSantiago, E.I. Ortiz-
Rivera 1 Describe proposes a topology for single-phase two stage grid connected solar
photovoltaic (PV) inverter for residential applications. Our proposed grid-connected power
converter consists of a switch mode DC-DC boost converter and a H-bridge inverter. The
switching strategy of proposed inverter consists with a combination of sinusoidal pulse
width modulation (SPWM) and square wave along with grid synchronization condition.
The performance of the proposed inverter is simulated under grid-connected scenario via
PSIM. Furthermore, the intelligent PV module system is implemented using a simple
maximum power point tracking (MPPT) method utilizing power balance is also employed
in order to increase the systems efficiency
 E. Babaei and S. H. Hosseini,2 state an advanced topology for cascaded multilevel
inverter using developed H-bridges is proposed. The proposed topology requires a lesser
number of dc voltage sources and power switches ,which results in decreased complexity
and total cost of the inverter. Moreover, a Bee algorithm(BA) to determine the magnitude
of dc voltage sources is proposed. It is used to solve the transcendental equations for
finding the switching angles. This algorithm can be used for any number of voltage levels
without complex analytical calculations. Simulation results for 15-level inverter verify the
validity and effectiveness of the proposed algorithm
.
 Pereda and J. Dixon,3 Express about Multilevel inverters are in state-of-the-art power
conversion systems due to their improved voltage and current waveforms. Cascaded H-
bridge (CHB) multilevel inverters have been considered as an alternative in the medium-
voltage converter market and experimental electric vehicles. Their variant, the
asymmetrical CHB (ACHB) inverter, optimizes the number of voltage levels by using dc
supplies with different voltages. However, the CHB and ACHB inverters require a large
number of bidirectional and isolated dc supplies that must be balanced, and as any
multilevel inverter, they reduce the power quality with the voltage amplitude.

.
 L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats4
explain Multilevel converters have been under research and development for more than
three decades and have found successful industrial application. However, this is still a
technology under development, and many new contributions and new commercial
topologies have been reported in the last few years.
 ADiaz, R. Saltares, C. Rodriguez, R. F. Nunez, E.!.OrtizRivera, and 1. Gonzalez-
Llorente,5 Proposed "Induction motor equivalent circuit for dynamic simulation," Until
now the use of equivalent circuit for induction motor has been limited for steady state
analysis. The equivalent circuits for dynamic simulation proposed until now, are not able to
obtain the transient response of the induction motor, because they lack of mechanical
component representations. Complex non-linear matrices are used instead. Here electrical
analogy of mechanical system is integrated with d-q equivalent circuit derivates from the
stator frame of reference to create a complete equivalent circuit for three-phase induction
motor which is suitable for dynamic simulation. Finally this paper presents results that
validate the proposed circuit by comparing it with that obtained with mathematical models.
 K. Wang, Y. Li, Z. Zheng, and L. Xu,6 Proposed "Voltage balancing and fluctuation
suppression methods of floating capacitors in a new modular multilevel converter,"
Modular multilevel converter (MMC) is a newly emerging multilevel topology for high-
voltage applications during recent years. In this paper, a new MMC is proposed, and the
structure and operating principle are analyzed. Owing to the cascaded basic cells without
multi-winding transformer, the voltage balancing of floating capacitors must be considered.
However, the voltage fluctuation also exists, and theoretical analysis indicates that the
amplitude is inversely proportional to the fundamental frequency. This paper has proposed
a voltage-fluctuation-suppression method which can reduce the amplitude of the voltage
fluctuation in low-frequency region. It can also be used in motor driving with pump/blower
like load at low frequency and improve the start-up performance significantly. A low-power
three-phase five-level prototype is designed and built up to demonstrate the validity of this
method.

 L.M Tolbert, F. Z.Peng and T. G Habelter, Proposed "7 states multilevel power converters
as an application for high-power and/or high-voltage electric motor drives. Multilevel
converters: (1) can generate near-sinusoidal voltages with only fundamental frequency
switching; (2) have almost no electromagnetic interference or common-mode voltage; and
(3) are suitable for large volt-ampere-rated motor drives and high voltages. The cascade
inverter is a natural fit for large automotive all-electric drives because it uses several levels
of DC voltage sources, which would be available from batteries or fuel cells. The back-to-
back diode-clamped converter is ideal where a source of AC voltage is available, such as in
a hybrid electric vehicle. Simulation and experimental results show the superiority of these
two converters over two-level pulse width-modulation-based drives.
 Ebrahim Babaei,Somayeh Alilu, and Sara Laali8, brif a new general cascaded multilevel
inverter using developed H-bridges is proposed. The proposed topology requires a lesser
number of dc voltage sources and power switches and consists of lower blocking voltage on
switches, which results in decreased complexity and total cost of the inverter. These abilities
obtained within comparing the proposed topology with the conventional topologies from
aforementioned points of view. Moreover, a new algorithm to determine the magnitude of
dc voltage sources is proposed. The performance and functional accuracy of the proposed
topology using the new algorithm in generating all voltage levels for a 31-level inverter are
confirmed by simulation and experimental results.

Chapter : 3
PROBLEM STATEMENT
Asymmetric voltage technology is used in the cascade H-bridge multilevel inverter to allow more
levels of output voltage, so the cascade H-bridge multilevel inverter is suitable for applications with
increased voltage levels. Two H-bridge inverters with a dc bus voltage of multiple relationships can
be connected in cascade to produce a single phase seven-level inverter and eight power electronic
switches are used. In this project a new asymmetric Bi-directional converter topology which uses
contradictory ratios of dc voltage sources. This inverter having 3 bridges connected in series gives
different levels of output voltages without changing the circuit except the ratios of input voltages.
Switching of the converter is done by following the staircase control technique. Pulse width
Modulation technique can also be applied by appropriate calculation of the switching time period.

Chapter : 4
METHODOLOGY
A converter consisting of twelve modules with a DC Sources will result in huge number of diverse
output voltage levels. This composition will be compared with the predictable approach with
identical DC voltage sources. Two different control methods for a single phase converter are
offered. Both algorithms imagine a steady sampling interval of the control, Ts. The first one uses a
stable switching state during a full sampling interval (step or staircase method), whereas the second
one is implemented with a Pulse Width Modulation (PWM method). Both methods receive that the
DC source voltages are not steady but variable in time. The definite voltages on the capacitors are
therefore calculated, and the phase voltage vector Vii is created. In order to compute all attainable
output voltages Vol, the phase voltage vector is multiplied with all possible switching states SI.
This results in an unsorted vector containing all feasible output voltages.
Fig- 4.1 (1) H Bridge Circuit
This inverter having 12 bridges connected in series gives different levels of output voltages without
changing the circuit except the ratios of input voltages. Switching of the converter is done by
following the staircase control technique. Pulse width Modulation technique can also be applied by
appropriate calculation of the switching time period.

Chapter : 5
HARDWARE DESCRIPTION
5.1 INVERTER CIRCUIT
`
S1
S
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
9V9V 9V
R
D D D D D D
Fig- 5.1 (1) Inverter Circuit
5.2
MCT2 OPTO COUPLER
Fig- 5.2 (1) Opto Coupler Symbol

Absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)
 Input-to-output voltage: MCT2 . . . . . . . . . . . . . . . . . ... . . . . . .. . . . . . . . . 1.5 kV
 MCT2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • 3.55 kV
 Collector-base voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 70 V
 Collector-emitter voltage (see Note 1) . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 30 V
 Emitter-collector voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
 Emitter-base voltage . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7 V
 Input-diode reverse voltage . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 V
 Input-diode continuous forward current . . . . . . . . . . . . . . . . . . . . . …. . . . . . 60 mA
 Input-diode peak forward current (tw ≤ 1 ns, PRF ≤ 300 Hz) . . . . . . . . . . . . . 3 A
 Continuous power dissipation at (or below) 25°C free-air temperature:
 Infrared-emitting diode (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW
 Phototransistor (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW
 Total, infrared-emitting diode plus phototransistor (see Note 3) . . . . . . . . . . . 250 mW
 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . .–55°C to 100°C
 Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. –55°C to 150°C
 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . .. . . 260°C
 Stresses beyond those listed under “absolute maximum ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at
these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied.
 Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
NOTES:
1. This value applies when the base-emitter diode is open-circulated.
2. Derate linearly to 100 °C free-air temperature at the rate of 2.67 mW/°C.
3. Derate linearly to 100 °C free-air temperature at the rate of 3.33 mW/°C.

Table 5.2 (1) Characteristics of Opto Coupler Used
5.3 SWITCHING TRANSISTOR NPN
Table -5.3 (1) PIN details
Fig- 5.3 (1) Figure & Symbol

Table -5.3 (2) Specification
5.4 SWITCHING TRANSISTOR PNP
fig -5.4 (1) Symbol
Table -5.4 (2) Specification details

5.5 Switch Used-MOSFET
Fig- 5.5 (1) MOSFET
Table 5.5 (1) Specifications of MOSFET

Table 5.5 (2) Characteristics of MOSFET
5.6 Circuit-Cum-Block Diagram

Fig- 5.6 (1) Project Model (disconnected from supply)
Fig- 5.6 (2) Project Model (Connected to the supply) and is under test

Fig- 5.6 (3,A) Driver Circuit
Fig- 5.6 (3,B) A Clear view of the Driver Circuit

Fig- 5.6 (4) A Clear view of the inverter Circuit

Chapter : 6
SOFTWARE DESCRIPTION
6.1 MICROCONTROLLER [PIC 16F877A]
Fig- 6.1 (1) Pin Diagram and Features of Microcontroller used [PIC16F87XA]
Fig- 6.1 (2) Pickit – 3 used to load Program into the Micro controller

Fig- 6.1 (3) PIC16F87XA

6.1.1 MICRO CONTROLLER PIN DETAILS
Fig 6.1.1 (1) port details [pic16f87xa]

6.2 Code in MP-LAB software to program the micro-controller
/*
* File: Code.c
* Author: Vignesh
* Project : Multilevel Inverter : 7Level
* Created on 22 April, 2016, 3:42 PM
*/
#include "Configuration.h"
#include <pic16f877a.h>
#include <stdio.h>
#include <stdlib.h>
#define S1 PORTBbits.RB0
#define S9 PORTDbits.RD0
#define _XTAL_FREQ 20000000 // Operating Crystal freaquency
#define __delay_us(x) _delay((unsigned long)((x)*(_XTAL_FREQ/4000000.0)))
#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ/4000.0)))
void main()
{

TRISB = 0;
TRISD = 0;
while(1)
{
__delay_ms(2);
S1 = 1;
S2 = 1;
S6 = 1;
S10 = 1;
__delay_ms(1);
S5 = 1;
__delay_ms(1);
S9 = 1;
__delay_ms(2);
S9 = 0;
__delay_ms(1);
S5 = 0;
__delay_ms(1);
S1 = 0;
S2 = 0;
S6 = 0;
S10 = 0;
__delay_ms(4);
S3 = 1;
S4 = 1;
S8 = 1;
S12 = 1;
__delay_ms(1);
S7 = 1;
__delay_ms(1);
S11 = 1;
__delay_ms(2);

S11 = 0;
__delay_ms(1);
S7 = 0;
__delay_ms(1);
S3 = 0;
S4 = 0;
S8 = 0;
S12 = 0;
__delay_ms(2);
}
}
6.3 Switching Pulses
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12

Chapter : 7
IMPLEMENTATION
Hybrid Multilevel Inverter was introduced by means of all 3M possible output voltages, where M is
the number of modules allied in series. Though this inverter uses extremely different DC voltage
sources in the relation of 1:3:9 etc. In distinguish, the DC voltage sources consider in this paper are
still exceptionally close to each other, they fluctuate only by ±20 %. The quantity of cells in
sequence determines the number of output levels. 3M= 27 switching states SI ,when M= 3 cells.
With similar DC voltages, there are numerous switching states that create the same output voltages,
resulting in 2.M + 1 = 7 different phase output voltage levels. Uneven DC source voltages direct to
an improved number of different output voltage levels. The maximum number of levels is 3M = 27.
With the DC source voltages distributed as Viii :Vi12 : Vil3 = 1 Voc : 3Voc : 9Voc, all the
dissimilar output voltage levels are consistently spaced. The aim of such an inverter (Hybrid
Multilevel Inverter) has the disadvantage that the preliminary modularity is vanished. Each module
must be intended for the equivalent voltage class. When the DC source voltages are uneven but only
±20 % unlike from each other, the number of different output voltage levels is also superior. As an
instance, we believe a case where one cell has 100 % of its nominal DC voltage, other has 120%
and the third one has 80%. The DC source voltages are in relation of 4:5:6 in this scheme. As can be
seen, the voltage levels are approximately the same as in the 1:3:9 case, apart from some levels not
there at high complete values of output voltage. In order to consider the possible benefits of using
unlike DC voltages, the 4:5:6 relation is used as an instance in the following part. For a first
estimation it is abandoned if these differences are introduced by the moment behaviour of the DC
voltages, or if they are introduced by design and thus can be supposed to be stable. The second case
is considered at this time for the sake of simplicity. The below figure shows the output wave forms
the proposed asymmetrical converter. It is clearly seen that the level of inverter varies with the
change in the ratios of input voltage. The inverter gives 7 level output voltage when the ratio is 1: 1:
1, while it gives 23 level output voltage when the ratio is 4:5:6 and it gives 27 level output voltage
when the ratio is I :3:9. This inverter having 3 bridges connected in series gives different levels of
output voltages without changing the circuit except the ratios of input voltages. Switching of the
converter is done by following the staircase control technique. Pulse width Modulation technique
can also be applied by appropriate calculation of the switching time period

Fig 7 (1) Asymmetrical cascaded multilevel inverter topology with different ratios of input voltages

Fig- 7 (2) Proposed Cascaded multilevel inverter circuit

7.1 CONTROL SCHEME
This section will discuss in detail a converter consisting of three modules with a DC voltage
ratio of Vi11:Vi12:Vi13 = 4Voc : 5Voc : 6Voc. As can be seen in Fig. 3, this results in a huge
number of diverse output voltage levels with an incredibly good voltage resolution. This
composition will be compared with the predictable approach with identical DC voltage sources, and
with the Hybrid Multilevel Inverter using a 1:3:9 voltage relation. Two different control methods
for a single phase converter are offered. Both algorithms imagine a steady sampling interval of the
control, Ts. The first one uses a stable switching state during a full sampling interval (step or
staircase method), whereas the second one is implemented with a Pulse Width Modulation (PWM
method). Both methods receive that the DC source voltages are not steady but variable in time. The
definite voltages on the capacitors are therefore calculated, and the phase voltage vector Vii is
created. In order to compute all attainable output voltages Vol, the phase voltage vector is
multiplied with all 311 possible switching states SI. This results in an unsorted vector containing all
feasible output voltages.
Fig- 7.1 (1) Output of different voltage ratios

Table 7.1 (1) Switching sequence of inverter

RESULTS
Fig A- output waveforms of 7-level inverter shown

Fig B- A clear view of the waveforms
The below figure shows the output wave forms the proposed asymmetrical converter. It is clearly
seen that the level of inverter varies with the change in the ratios of input voltage. The inverter
gives 7 level output voltage when the ratio is I: 1: I, while it gives 23 level output voltage when the
ratio is 4:5:6 and it gives 27 level output voltage when the ratio is 1:3:9. This inverter having 3
bridges connected in series gives different levels of output voltages without changing the circuit
except the ratios of input voltages. Switching of the converter is done by following the staircase
control technique. Pulse width Modulation technique can also be applied by appropriate calculation
of the switching time period.

Fig C- Output waveforms of 7 level inverter
Fig D- Total Harmonic Distortion (THD) of 7 level inverter

CONCLUSION
The results show that in this project 3- phase 7-level asymmetrical cascaded H-bridge
inverter are studied. The output voltage of three phase Asymmetrical 7-level asymmetrical CHB
gives 12.56% THD without PWM technique. The output is consists of minute number of harmonics
and increased output voltage quality. Finally the proposed system is connected to CRO to get the
waveforms.
The output can be connected to devices like induction motor etc. for future industrial and
automotive applications.
Multilevel inverters are very interesting for high voltage applications, energy conversion and
considerably improve the output voltage quality. This project has proposed a new topology of the
cascaded inverter called Asymmetrical 7 level inverter. The main advantages of the Cascaded multi
level inverters are improve the output voltage quality, reduced number of switching devices,
operates in symmetric an asymmetric states existence of different algorithms for calculating of
magnitudes of DC voltage sources and freedom action to designer for design multilevel inverter
small on-state voltage drop and conduction losses reduction of dv/dt stresses on the load

SCOPE & DEVELOPMENT
INNOVATIONS
• The power module and digital controller interface is developed as separate units with provisions
for change of configuration or up gradation in power module as well as hardware interface to make
it suitable for load up to 1.5 KW.
• The control signals are developed using combination of MATLAB/SIMULINK, code composer
studio and emulator which eliminates writing a code for the software. The technique can be used by
the user who is not proficient in programming.
FUTURE PLANS FOR EXTENSION
• Software can be generated for closed loop system.
• Circuit of HMLI with capacitors as voltage source can be used as other HMLI topology. For
portable HMLI regulated power supply can be replaced with batteries and rechargeable voltage
source, which may be taken as future project.
• The power module can be modified to realize other hybrid multilevel inverters such as
symmetrical or asymmetrical hybrid multilevel inverter or half bridge multilevel inverter for single
phase or three phase and modulation techniques developed in this project can be used with minor
modifications.
• It is possible to realize different power electronics system applications such as drives, EV.
• As already stated it is possible to modify the power and control circuit so that HMLI can be used
for load more than 3 KW otherwise same power and control circuit can be used.
• With some small modification other topologies can be developed for HMLI.
• It is possible to implement this system with digital signal controller and make the system more
cost effective. Chapter 9 Concluding Remarks and Future Scope 150
• Other modulation techniques can be applied to this system to reduce THD

PICTURES OF WORKING PROJECT MODEL
OUTPUT SEEN IN CRO

OBSERVATION OF THE OUTPUT

PROJECT TEAM WITH GUIDE

REFERENCES
 A Santiago-Gonzalez, 1. Cruz-Colon, R. otero-De-leon, V. lopezSantiago, E.I. Ortiz-
Rivera, " Thre phase induction motor drive using flyback converter and PWM inverter fed
from a single photovoltaic panel," Proc. IEEE PES General Meeting, pp. 1-6,20 II.
 M. A Vitorino et aI. , "An efficient induction motor control for photovoltaic pumping,"
IEEE Trans. Industrial Electron., vol. 54, no. 4, pp. 1162-1170, April. 2011.
 ADiaz, R. Saltares, C. Rodriguez, R. F. Nunez, E.!. OrtizRivera, and 1. Gonzalez Llorente,
"Induction motor equivalent circuit for dynamic simulation," Proc. IEEE Electric Machines
and Drive Conference, (lEMDC ), May 2009.
 E. Babaei and S. H. Hosseini, "Charge balance control methods for asymmetrical cascade
multilevel converters," in Proc. ICEMS, Seoul, Korea, 2007, pp. 74-79.
 K. Wang, Y. Li, Z. Zheng, and L. Xu, "Voltage balancing and fluctuation suppression
methods of floating capacitors in a new modular multilevel converter," IEEE Trans. Ind.
Electron., vol. 60, no. 5, pp. 1943-1954, May 2013.
 L.M Tolbert, F. Z.Peng and T. G Habelter, "Multilevel Converter for large electric drives,"
IEEE trans.lnd.Appl.VoI35, no. I, pp. 36-44, Jan/Feb.1999.
 K. Nakata, K. Nakamura, S. lto and K. Jinbo, "A three level traction inverter with IGBTs
for EMU", in Conf.Rec.lEEE Las Annu.meeting, 1994, voU, pp. 667- 672.
 AJidin,N.R, N.R, N.R. N. ldris, AH.M. Yatim, t. Sutikno and E.Elbuluk,"An optimized
switching strategy for quick dynamic torque control in DTC-hysteresis-based induction
machines, IEEE trans.lnd.Electron. vo1.58, no.8,pp 3391 3400,Aug. 2011.
 E. Babaei, "A new cascaded multilevel inverter topology with minimum switches," IEEE
Trans.PowerElectron. Vol 23, no.6, pp. 2657- 2664, Nov. 2008.

 E. A Mahrouset al., "Three-phase three-level voltage source inverter with low switching
frequency based on the twolevel inverter topology," Electr.Power Appl., vol. I, pp. 637-
641, 2007
 M. F. Kangarlu and E. Babaei, "A generalized cascaded multilevel inverter using series
connection of submultilevel inverters," IEEE Trans. PowerElectron., vol. 28, no. 2, pp. 625-
636, Feb. 2013.
 J. Pereda and J. Dixon, "High-frequency link: A solution for using only one DC source in
asymmetric cascaded multilevel inverters," IEEE Trans.Ind. Electron., vol. 58, no. 9, pp.
3884- 3892, Sep. 2011.

BE-EEE-8th sem project report for the project titled "Asymmetrical Multilevel Inverter for Higher output Voltage Levels”

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to BE-EEE-8th sem project report for the project titled "Asymmetrical Multilevel Inverter for Higher output Voltage Levels”

Similar to BE-EEE-8th sem project report for the project titled "Asymmetrical Multilevel Inverter for Higher output Voltage Levels” (20)

More from MOHAMMED SAQIB

More from MOHAMMED SAQIB (17)

Recently uploaded

Recently uploaded (20)

BE-EEE-8th sem project report for the project titled "Asymmetrical Multilevel Inverter for Higher output Voltage Levels”