.

1. STIL Test Pattern Generation Enhancement in Mixed
Signal Design
Nor Azura Zakaria, Amry Amudi
System Integration
Research and Development
MIMOS Berhad
Bukit Jalil, Kuala Lumpur, Malaysia
Mohd Zubir Khalid, Muhamad Khairol Ab Rani
Microelectronic Technology Department
MIMOS Berhad
Bukit Jalil, Kuala Lumpur, Malaysia
Abstract— This paper is about the process for generating
stuck-at test patterns in the Standard Test Interface Language
(STIL) format from mixed signal design (MSD) simulation. A
design flow and a methodology are presented for generating
STIL test patterns that are ATPG-compliant with the scan test
procedure in the manufacturing test of digital blocks in an MSD
system-on-a-chip (SOC). Simulated waveforms are sampled to
generate raw test patterns, which are then converted by an
automation program into STIL test patterns that is ATPG-
compliant. This work was already successfully implemented at
MIMOS Berhad and stuck-at testing has successfully passing
100%.
Keywords—stuck-at fault; STIL test pattern; mixed signal
design; ATPG compliant;
I. INTRODUCTION
Previous research discussed the test method to test analog
blocks using an automation strategy for analog verification
using Analogue Test Wrappers [1,3]. Although there are many
software tools that can capture and convert digital patterns to
an ATE(Automaton Test Equipment)-compatible format, no
CAD( Computer Aided Design) tool is available today that can
perform stuck-at testing on the analog mixed-signal test
design[4]. There is no ATPG (Automated Test Pattern
Generation) tool that able to generate STIL test pattern by
reading MSD. This stuck-at testing uses scan chains as a test
platform which is developed in the design. To enable scan
testing and analog testing can be driven smoothly, one test
module with its test control system is designed to ensure the
test pattern is safely convey from scan in to scan out to the
ATE tester. The MSD test access platform development
includes preparing test architecture at top level. There will be
an additional test procedure to generate test pattern at chip
level, where at top level there is a test access system managing
on and off able to accommodate MSD behavior instruction set
from digital level to chip level.
In this work, the flow of generating stimuli for running the
simulation from sub level of digital part up to MSD level. The
STIL is generate from MSD simulation waveform will be
described resulting an automation program which will be
explained further in the following section.
The remainder of the present paper is organized as follows.
Section II discusses background and motivation. In Section III,
presents Design Methodology applies in this work. In Section
IV, the experiment result demonstrate the technical works
practice the implementation of generating STIL test pattern on
MSD in the company. Finally, Section IV concludes the work.
II. BACKGROUND AND MOTIVATION
A. Background
Fig. 1. Conventional Flow of post layout test pattern generation
for manufacturing test
Recently there are several products in digital and analog
design equipped in one integrated circuit, also classified as
mixed signal designs (MSD), widely used in the market.
Moreover, the digital application in MSD uses approximately
50% of the die size or more which requires manufacturing
testing for digital design especially fabricated in deep
submicron process technology. There are few types of testing
specifically for analog module designs and for digital module
designs. Testing digital module design consists of two types of
test such as functional testing and manufacturing testing. The
challenge in mixed design industry is generating test pattern
that is vital to success.

2. Some researchers have found that generating test programs
for MSD devices is time-consuming, labor intensive and can
only be done on fabricated devices. As per described from
Figure 1, it is a hurdle whereby engineers need to test and
debug the STIL whether it matches with the simulation. More
or less, the possibility of failure is always there if there is a
missing vector that should be included between the chip level
propagated into the digital design. The dummy failures are also
expected to be occurred if the capture test pattern is not ready
at some test event. One example is shown in Fg.2, where there
is a propagation delay at the output signal at the edge of
transition of Scan Enable, SE. Thus, the output signal at this
edge should be ignored either after or before one clock cycle at
this event. The test pattern should be masked to be observed
since the capture test pattern is not ready. The condition of the
test pattern is not ready to observe is occur many times and if
the program is missed to handle the condition, probably we
will face the mismatches.
Fig. 2. Propagation delay on the output at the edge of transition SE
B. Motivation
There is a motivation to generate an ATE test pattern that is
compliant with the ATPG test procedure. The controllability
and observability the issues must be identified and resolved at
an early stage to ensure the ramp up time and initialization test
procedure is ready to access digital module to test stuck-at test
patterns particularly for digital modules in MSD testing.
Fig. 3. Proposed design flow of STIL test pattern generation for
MSD[4]
The process of generating STIL test patterns as shown in
Fig. 3 is the proposed design flow of STIL test pattern
generation for MSD. The vector test generation is based on
sampling time determined while reading the pass simulation
result at the post layout stage simulated in one of mixed signal
simulator. The final STIL generation program is an ATPG
compliant STIL test pattern that will be passed to Automated
Test Equipment.
III. DESIGN METHODOLOGY
As mentioned in Section II, the method in generating a
STIL test pattern for MSD, comprises the steps of simulating
spice analog signal, conversion of analog to digital simulation,
the steps of automation program to generate STIL test pattern
from a translated vector and modifying translated vector to
STIL format. Finally based on the proposed automation
program the generated STIL test pattern that is ATPG
compliant will be generated.
A. Test Vector Translation
Fig. 4. Flow chart of vector Translation
The simulated signals from the CAD tool are read and
saved into binary signals captured by the CAD tool. The
collection of the vectors on each signals is conducted,
according to sampling period and the consecutive testing time.
A simulation value is probed based on consecutive testing time
from values of 0 or 1 of a sampling period from the beginning
to the end. The vector translation flow is as described in Fig 4.
ID in this case present each input signal file and each output
signal with simulated data from beginning to the end.
Accordingly, each data file, signal file or text file present
one signal and contain the information of period simulation as
well as its simulation data of either 0 or 1. Each of these binary
signals can then be saved as a single database file. This list of
vectors will be divided to a set of binary signals which contain
the input and the output simulated signals referring to a
particular event time. Single database with their own file ID
consisting the list of input signal e.g a, b, c and etc. and the list

3. of output signals e.g o1,o2,o3 and etc. This is illustrated in Fig.
5. One test program is developed to read in all the file ID
which is ready to be converted into the STIL test format.
Fig. 5. Flow Chart of STIL Pattern Generation
B. ATPG Compliant Test Pattern Generation
As shown from Fig. 6, there is a test program platform that
is built to generate STIL ATPG. The test program called STIL
ATPG generator consists of a STIL reader and a STIL writer.
The STIL writer with an ATPG enhancement feature will add
in the parameter of the signals involved and the test procedure
to place a header to the STIL test file.
Fig. 6. STIL ATPG Test Pattern Generator
During STIL test pattern generation, as illustrated in Fig. 7
each line of test vectors can have a list of test vectors started
with V appended with “{“, followed by “ALL=”, followed by
“binary test vectors of either “0” or “1”, which then the
represent list of input signals and followed by the list of
expected output signals comprising list of “H” or “L”. The
expected output of “H” means a high voltage and “L” means a
low voltage. V also indicates one sampling time to input all test
vectors into the primary inputs of DUT that needs to be tested
and ended by “}” per one line of test vectors. As an example,
the test vectors can start with 0 nanoseconds, and the list of test
vectors can be updated for every test cycle, for example 25
nanoseconds, whereby the cycle data of test vector may change
every 25 nanoseconds. The vectors which already collected to
one file is then translated by the in-house program which
namely as OLD STIL as illustrated in Fig.7. The new STIL
will be generated by STIL Writer after the enhancement feature
is extended.
In order to accommodate the STIL test pattern with the
ATPG test procedure and to avoid mismatches at certain time,
a step of masking test pattern based on the developed scan test
procedure can be applied using ATPG enhancement features.
The sampling data captures only at the former edge of the
sampling period, observing the expected output at a certain
cycle.
Fig. 7. One of Comparison of old STIL vs new STIL with ATPG
Procedure
Note that the final test pattern in the STIL format can be
generated for MSD signals to be passed to the tester, in order to
be used in ATE. After all signals are processed and updated,
the test pattern can be written into a STIL file. The project
name can be used as the STIL file name for easy reference.
Initially, any header can be inserted into the STIL file for a
quick user reference. By using all information available, the
signal's list block can be printed with its direction, followed by
a signal group block, timing waveform block that consists of
all signals with their possible values, and pattern execution
blocks. Finally, the pattern for each signal can be printed based
on the signal hash array into the same STIL file. With that, the
initial STIL test pattern file could be completed. Accordingly,
an updated STIL test pattern can be eventually produced,
wherein such updated STIL test pattern is compliant with the
proposed scan test procedure for MSD chip.
C. ATPG Rule and Test Procedure in STIL Test Pattern
Generation
The following are the test procedure that need to be
managed to enhance the STIL feature with the sequence of the
test vector presenting the ATPG test procedure. This test
procedure can be used in the other design if those steps are
practice straightforward.
1) ATPG 1: Ramp up time ( time duration for SoC of MSD
from Power On Reset to activate signals), after the Design
under test is power up after Power on reset (POR) some signals
need to set to be 0, and certain signals must be arranged to
shutdown analog signals and generate 0s to digital blocks. This
is need to ensure from the chip level architecture the test mode

4. of testing stuck-at fault testing is accessed safely into the
digital module.
2) ATPG 2: Initialization period after ramp up time, will
initiate and indicate the testing of the design under test for
stuck-at test patterns just started, this scan enable pin, SE=0,
reset pin, RST=0, and clock pin, CLK off .
3) ATPG 3: In testing stuck-at faults, a shifting mode period
will have two condition based on the ATPG test pattern
generation that is produced by the ATPG tool where :
a) when SE=1, RST=1, Primary Output, PO is measured
only at one or more cycle after clock transition; (CLK=0-1-0,
RST =1, SE=1 )
b) When CLK=0, RST 0-1, PO is not measured when
RST is 1.
4) ATPG 4: In testing stuck-at faults, capture mode occurs
when SE=0, RST= 1, PO measured only at RST is high, but
not measure or observe when it first initial state. This is call
capturing defect data through the logic gates directed to PO.
Fig. 8. Some of STIL Test Pattern Comparison between before customize and after customize based on ATPG Procedure
5) ATPG 5: Capture mode to shifting mode (load /unloading
data) when SE=0-1, RST= 1, CLK-0, PO is not measured
when SE is 1.
6) The outputs are set to ‘don’t care’ or ‘not measured’, “X”
when there is a signal transitions for reset or scan enable or
clock signal. Don’t care means, the propagation data in
progress, between shifting and capture mode or between initial
state to normal state or between loading or unloading mode.
Fig. 8 shows some of the example adding ATPG procedure to
add in the condition of ‘don’t care’ where the exception the
tester to observe the output value. The original STIL test
vector which obtain from simulated signals is not specify any
value that should be masked, ‘X’ed.
The test procedure as explained above can be summarized
from ATPG1 to ATPG 4 in general. ATPG 1 is a ramp up time
(SOC of MSD from power on reset (POR) to activate signals),
where all values are set to be “0”, and certain signals are
configured to shutdown analogue signals and the analog design
block stimulus 0s to the digital design block. ATPG 2 is the
initialization period after ramp up time, in which SE=0, RST=0
and CLK is off.
ATPG 3 is the shifting mode period when SE=1, PO is
measured when CLK is “1” or if the CLK is transition from “1”
to “0” or CLK is “0”, PO is not measured or if there is a
transition from SE=1 to SE=0 or SE=0 to SE=1, PO is not

5. measured; while ATPG 4 is the capture mode when SE=0, PO
is measured when CLK is “1” or if the CLK is transition from
“1” to “0” or CLK is “0”, PO is not measured or not measured
at reset transition . This is referred to as capturing defect data
through the logic gates directed to PO.
The masking test pattern is also checked at any transition of
reset from “0” to “1” or “1” to “0”, primary output (PO) is not
measured. When PO is not measured, the PO value will be
marked as an “X”.
IV. EXPERIMENTAL RESULTS AND DISCUSSIONS
The work is conducted based on a mixed signal design
fabricated in the 0.18 micron SILTERRA CMOS process
technology. Full scan flip flops were implemented in digital
core modules in the MSD in MIMOS Berhad for scan testing
with one scan chain consisting 1342 flip flops implemented to
test manufacturing defects. Testing of stuck-at faults for each
node of the digital parts requires certain setup to ensure the test
can be done successfully. Test mode specification for various
configurations must be prepared such as for analog to digital,
A/D and digital to analog, D/A converter testing, scan testing,
power on reset testing, voltage bandgap testing, oscillator
testing and other related test modes. As shown in Fig. 9, it was
designed with one test enable pin, Test Enable that connects to
a few control units for a separate test mode configuration to
control both analog and digital signals. The test enable pin
together with a specific setting is used to ensure proper control
for certain application. The test enable pin is a digital pin that is
connected to the ATE tester on the outside of the board. A
control signal and a power shifter that sources different
voltages are also designed to ensure the test engagement can be
driven safely.
Some constraint pins and glue logic are prepared to ensure
the digital part module of MSD chip is testable and controllable.
Fig. 9. MSD In House Test Architecture
ATPG Simulation is done at two levels, one is at the digital
top of the digital core module and another simulation is run at
the full chip level at the MSD module using a mixed signal
design simulator.
As depicted in the Fig.10, the flow chart shows the process
needed to generate a test pattern that can be used at the full
chip level that contains MSD circuitry. Starting from the
verilog test bench and test pattern generated by ATPG tools, a
digital simulation is executed to generate a waveform file in a
value core dump, VCD and a wave log format,WLF formats.
The VCD file is then converted into a simulated circuit, CIR
format using a PERL script. CIR format is used as an input
stimulus in Questa ADMS simulation tool. The waveform
output from the simulation is saved in a WDB file format.
WDB file format is the transient simulation of circuits
characterized in frequency format.
At this stage, the full chip simulation is run using the same
input stimulus as in the earlier digital simulation. Therefore, the
digital output from this mixed signal simulation must match
with the initial digital simulation output. In order to verify this,
a waveform comparator tools is used. The tool can read both
.wdb and .wlf. The tool will compare both waveforms and flag
any mismatches. If there is no mismatch it means that the
ATPG simulation at the chip level is successfully tested and
can be used to pass to the ATE tester.
Fig. 10. Flow Chart of STIL Generation of Scan Testing
in MSD
The simulated output in analog value will be change to the
digital output. To have a digital stimulus of 25ns, each signal
will be probed and presented in text files. In this text file, each
signal of 0 or 1 will be computed by our test automation
program to generate STIL test patterns that comply with the
ATPG test procedure as discussed in previous section. The
STIL test pattern were successfully developed based on the
simulation captured from the MSD simulation on chip level.

6. This industrial design has been taped out three times and
the STIL test patterns were generated using the same flow.
Results are as follows:
1. First tape-out manufacturing test – almost 98% is
successfully passed. The 2% failure is ambiguous and
inconsistency results.
2. Second tape out manufacturing test – passed
successfully after finding mismatches during test
pattern generation. After solving these mismatched, all
simulations passed.
3. Third tape out manufacturing test –passed.
V. CONCLUSIONS
The paper has demonstrated the flow of generating STIL
test pattern to test stuck-at faults for digital modules in a MSD
SoC. The flow covers the test vector translation from simulated
waveforms to generate STIL test patterns after test vectors are
samples based on the desired sampling time. The present work
provides an ATPG test procedure to ensure the output of final
STIL test pattern is ATPG compliance.
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