GaAs PCM or WAT data to device model using Neural Network to predict device performance and yield and also target and verify device to process centering.

1. MICROELECTRONICS READING FACILITY
Subject Updated paper from 1995/6 presented at MTTS test conference Group: HSPL
Date: June 21, 2001
From: Laird R. Snowden, Jr.
Loc: 20A313C, Bldg 20
Dept: 50N6K9100
Ext: 3134
Email: lsnowden@agere.com
PROCESSCONTROLMONITORTODEVICEDATACORRELATION
For Long Haul Sonet Codes
Laird R. Snowden, Jr.
AT&TMicroelectronics
GaAs Wafer Test
ABSTRACT
PCM to device modeling is used as an aid in selecting wafers for testing to meet high throughput
demands, check for design centering and to facilitate lot starts to meet demand based on early
information provided from PCM testing of the wafer during wafer fabrication. Additionally it is
used as an FMA flag, for wafers that have low yield when they are predicted to have high yield.
Wafers have limits on PCM parameters, it was found, however, that these limits did not always
guarantee a good wafer.
Typically, designs are created with a nominal FET or Transistor model that is representative of
the process. After the design is completed, there is no guarantee that every wafer produced in the
process will match the model used for the device design. Here in lies a conundrum. What
happens when wafers come in with little or no yield? What parameter in the process is causing
the devices to fail? What is needed is a model, which can accept as input the outputs of PCM RF
and DC testing and forecast device parameters such as gain.
When HSPL wafers arrive from the foundry, they are typically either fully RF device tested or
sample tested for Incoming Inspection. In the event that the yield is low, the question is asked
“what is wrong? “ Is it the test set ? Are the wafers bad? Is the design centered ? Were there
mechanical problems (metalization etc.), Are all the wafers bad ?. It would be useful to have a
predictive model which accepted as inputs, PCM values.
GaAs models tend to be empirical in nature (other than diode drop). In the event that the PCM
data shipped with the wafer contain all of the inputs required by the design simulator, then they
may be used to predict device performance. This is usually not the case however.

2. Another way to create a predictive model of the device, is to create a model from PCM data and
device data. In this instance data from the RF and DC PCM files is spliced together with data
from the device sites that surround a PCM site. If the electrical characteristics of the device are
dependent on the electrical characteristics of its building blocks (transistors, reistors, capacitors
and inductors) then there should be a strong correlation. However, no one parameter may fully
explain the device performance. One PCM parameter can be offset be another. An example is
variation in sheet rho combined with a deviation (from the model used in the circuit design) in
gate length. A model can be expected to work better if it includes all of the PCM properties
(independent variables) which can uniquely cause the designed device to change in performance
(dependant variables).
Many of the PCM measurements are non-orthogonal. An example is Gm at 1ma/mm, Gm at 20
ma/mm and Gm at 50 ma/mm. A draftsman plot of these grouped values showing Gm10 Vs
Gm20 may be on an identical slope except for some devices in the tail. It is important to include
the tail information since this becomes significant if multiplied by many parameters.
The first step is to select devices surrounding a PCM site. Devices that may have mechanical
failures (measured values that are outside the probability error lines ) should be excluded along
with catastrophic failures. The ratio should be noted for further study into defect density if it is a
significant yield loss.
There are several considerations:
1) Devices may be bad as the result of mechanical failures in the process. Examples of this are
open vias, shorted traces (metal lift-off). Failures of this type tend to be catastrophic.
2) Devices may fail due to variances in the electrical characteristics of the devices. These are
determined by the components from which the device is built such as transistors, resistors,
inductors and capacitors. The characteristics of these constituent components are quantified
in PCM (Process Control Monitor) testing and include such things as barrier height, RF Gm
(extrinsic) Gm(intrinsic(calculated from measured values), Ft, GMdc at different current
densities, RF Rds, Vt, Idss, Cgs and so on. Additionally, variation in metalization can have
an effect on the PCM RF values, an example is gate width and gate length. Shorter gate
lengths could cause Gm to go down and Ft to go up. This indicates that process changes can
move more than one parameter. It also impies that there can be an associated ratio of
change between the individual parameters for a given process variation. The resultant
effects can therefore be non-linear and include crossing and non-crossing first order and
second order interactions. An interaction is the event of one independent variable modifying
the effect of a second independent variable on the dependant variable.
It is important to differentiate between parametric mechanical failures since these tend to be
uncorrelated to PCM measurements such as Gm, Rds etc..
Electrical parametric failures for long haul Sonet codes are such things as low gain where the
limits are placed on a continuous distribution and frequently bisect the distribution on designs
that are operating at or close to the theoretical limits of the process, or in some instances, of
physics (i.e. noise contribution). Frequently gas flow patterns over the wafer during processing
or epitaxial growth can seen in the electrical characteristics of a test FET if included in the

3. primary site with PCM measurements included in the primary test program. They may also
sometimes be seen in a 3D surface plot of promary device measurement (x,y position versus
paramter). These variations cause device performance to vary over the wafer. A process under
control tends to indicate a flat distribution with a steep roll off at the sides, however, there is risk
in assuming this without examining data.
Mechanical failures tend to be discontinuous catastrophic failures due to open vias, filaments,
dielectric punch through, incomplete metal lift off, etc. They can be systemic (mask scratches
that repeat in the same place in each reticle, area dependant (more prone in the outside ring) or
random. Yo/Do analysis is useful in quantifying this where it is a strong contributor to yield
loss..
What is needed is a model that can indicate from thePCM data that is shipped with each wafer, the
expected yield of a wafer (percent good) and the robustness of a wafer ( how far away from the
test limits the critical device parameters are).
Device RF performance and wafer yield is predicted from models using wafer PCM (Process
Control Monitor) data which is obtained during the fabrication of the wafer. RF device wafer
probe data is obtained using high speed production probe cards that equal or exceed package
performance. Modeling is done with Neural Network non-linear modeling and or Exceltm
linear
modeling. Non-linear data transformations may be included in the Excel model where they are
known. The AT&T ME GaAs LG1605DXB Limiting Amp was chosen for this study because it
has high gain and wide bandwidth (4 GHz). The two sets of data are combined in a relational
database and an empirical model is created. The PCM data is represented as the independent
variables in the model and the device data as the dependant variable. In a neural network model,
multiple inputs (independent variables) can be used and single or multiple outputs (dependant
variables) can be modeled. The accuracy of the model is greater if multiple single device output
models are created rather than one multiple output model. This is due to the risk of overtraining
one or more variables (with stronger correlation) in a multiple output model.
Software implemented Neuaral Network models are better at averaging out noise and dealing
with non-orthogonal data than algebraic models. They also do a better job extrapolating data
outside the experience range of the training set data used during creation of the model. Some
types of NN’s can be self training, continuous training as well .
Advantages of Neural networks:
1) Can deal with non-orthogonal data which includes information in the tail distributions.
2) Good at averaging out noise in measurements
3) Offers both linear and Nth order non-linear modelling even where there is no knowledge of
the non-linear relationships, handled automatically by 2nd
layer nodes.
4) Do not fail catastrophically when encounter data which is outside of the training set. The
model extrapolates along a sigmoidal transfere curve (assuming a sigmoidal transfere
function was used, which is most common). The best way to describe this is a ‘conservative
trend estimate’.
5) Models crossing and non-crossing interactions od independent variables.

4. Afetr creation, the model was deployed on a UNIXTM
server which also contained an InformixTM
relational database for PCM, Wafer and Package data when this work was done in 1995. A
calibration standard was implemented for the probe card with the same pad frame as the device
on a GaAs wafers.
I wrote a Unix script to parse the data and extract it to a flat file. The variables then ran through
an AWK script which contained the model to generate the predicted variable. The data was then
run through an S Plus script and an ACE report writer script to generate the plots.
The model is used by entering a wafer number, the script then gets the PCM data for that wafer
from the database and predicts device RF performance for each PCM site for which data exists.
The PCM data consists of active DC and RF and passive device data.
Results indicate good performance of the model with predicted gain closely matching measured
gain for different wafers with varying PCM distributions.
WAFER LAYOUT
Devices are fabricated on GaAs HFET Transistors. The wafer is laid out in reticules, each reticule has one or more
type of devices and one PCM site. The reticule is then stepped across the wafer. The PCM sites can thus provide
contour maps of the wafer surface. PCM sites contain active and passive devices, FETs, resistors, capacitors,
interconnect testers etc.. The FETs are measured at various points during fabrication. DC data is taken at Ohmic,
Final data is measured at completion and consists of both RF and DC measurements. The PCM data contains a row
and column identifier for each reticule. The devices are also identified by row and column number. No actual
numbers are placed on the devices, PCB’s or reticules. The numbers are virtual and are defined by a consistent
starting point on the wafer. Note that the new Texas TQS foundry includes clown numbers unlike the TQS Oregon
facility which declined my request to add clown numbers.
DATA
PCM PCM PCM PCM PCM
PCM PCM PCM PCM PCM
PCM PCM PCM PCM PCM
PCM PCM PCM PCM PCM
PCM PCM PCM PCM PCM
PCM PCM
PCM PCM PCM
PCM
PCM
PCM
PCM
PCM
PCM
PCM
device device device device
device device device device
device device device device
device device device
0,0
row,col
row,col
PCM
device device device device
device device device device
device device device device
device device device
RETICLE

5. The data is stored in a common relational database in three tables, being: PCM, Wafer and Package. The wafer
device data is identified by its row and column number. A virtual die number is created from the row and column
identity ( die number 114 would be located in row 1, column 14). A preprocessing algorithm uses the row and
column number to generate a reticule identity that matches the PCM identity, this reticule identity is added to the
wafer device data. The PCM and device data is spliced together using the common reticule identity and unloaded to
a new flat file for use in modeling. An example of an algorithm for extracting reticule number identity is:
VIRTUAL RETICULE CALCULATION:
xret= (die_num mod 100) div 5) - offset
yret= offset-(die_num div 100) div 5)
100 is used for 2 digit row and column designations, 5 is used for a 5 x 5 place row and column reticule.
Note:
Div and Mod are HP Basic commands that can be implemented in other programming languages with the Integer
command or in C by casting a float to an integer as follows:
<num> div <100> is equivalent to int(<num>/<100>)
<num> mod <100> is equivalent to <num> - (int(<num>/<100.) * <100>)
100 is used for up to 4 digit wafer numbers (2 digit row and 2 digit column numbers).
1000 would be used for up to 6 difit wafer numbers ( 3 digit row and 3 digit column numbers).
As an example 214 mod 100 = 14
214 div 100 = 2
DATABASE SPLICING SQL EXAMPLE:
SELECT pcm_table.wafer_num, pcm_table.param1, wafer_table.xret, wafer_table.yret, wafer_table.die_num,
wafer_table.param1
FROM pcm_table, wafer_table
WHERE pcm_table.wafer_num=“12345” and pcm_table.wafer_num=wafer_table.wafer_num and
pcm_table.xret=wafer_table.xret and pcm_table.yret=wafer_table.yret
SPLICED FLAT FILE EXAMPLE:
Wafer No PCM param1 x
reticule
y
reticule
die number wafer param1
987654 123.1 1 1 101 234.1
987654 123.1 1 1 102 234.2
987654 123.1 1 1 103 234.3
987654 123.1 1 1 104 234.4
987654 123.2 2 1 201 234.5
987654 123.2 2 1 202 234.6
987654 123.2 2 1 203 234.7
987654 123.2 2 1 204 234.8
Please note that this assumes that virtual reticle ID numbers are created and stored with test data to be matched to the
PCM ID numbers. The center of the reticle is the best location for alignment and focus and is reserved for primary
devices on the physical construct, but no such limitiations exist in the virtual.

6. An alternate way to do this would be to take the PCM die number and pick out the surrounding die numbers. Virtual
reticle ID numbers would need to contain an offset to center the PCM site in the reticle. The PCM site is usually
placed in the corner of the rteticle.
An example of this would be:
Selection SQL statement:
Where x.pcmtable>= (dienum.devicetable MOD 100) AND x.pcmtable<= (dienum.devicetable MOD 100)+1 AND
y.pcmtable>=(dienum.devicetable DIV 100)-1 AND y.pcmtable<=(dienum.devicetable DIV 100)
selects sites 401, 402 and 502 and PCM site 501.
MODELING
The independent variables for the model are the PCM RF, DC and passive component measurements. In the latest
model deployed, there are seven DC FET parameters Pinchoff, transconductance at various channel currents, etc),
two RF and one passive measurement. The dependent variables can be device RF and or DC measured data and or
yield. In the deployment described there was only one parameter (RF gain) which, empirically, was found to be the
key parameter for device yield. Modeling has been done with both multiple linear and non-linear Neural Network
modeling. The neural network has the advantage of being able to model non-linear interactions between dependent
variables as well as the primary non-linear responses, if they exist. In addition, Neural network models are not
impaired by non-orthogonal data.
The Neural network showed a 93% correlation coefficient, the Excel model indicated a 90 % correlation coefficient.
Since the Neural Network model (Predict by Neural Ware) was still in Beta site testing, the model extraction feature
was not yet fully implemented and the initial model was deployed using Excel, which has performed well.
1 2 3 4 5 6 7 8
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8

7. Untrained Neural Network model:
The underlying assumption in using this technique is th ability to relate PCM and device
measurements. The best place to do this is at the wafer level. Therefore it becomes
necessary to make accurate RF measurements on wafer. The following section deals with
the early development of RF Wafer probe.
STANDARDS
Two different standards were implemented. A standard was built on GaAs using coplanar waveguide with Air-
Bridge crossovers to insure the ground planes on either side are electrically tied together and equalized, 50 ohm load
and open and short sites. The pad frame of the standard matches the pad frame of the device. This standard was
characterized by Cascade Microtech and found to perform well. These were used to calibrate the S Parameter
analyzer.

8. EXAMPLE OF GaAs THROUGH CALIBRATION STANDARD. Open, short and 50 ohm standards were also
included.
The GaAs coplanar waveguide calibration through standard
provides adequate probe verification at 2.5 Gb/s. The combined
probe card and through insertion loss for both Cascade and GGB
cards was less than 1/2 dB at 2.5 Gb/s.

9. RF WAFER DATA COLLECTION
CASCADE MEMBRANE CARD GGB PROBE CARD
High Speed probe cards have been used, using both Membrane technology and
coaxial probe tips, both have worked excellently with performance equal to or
better than package performance for , in this case, a limiting amplifier with up to
45 dB of gain and bandwidth up to 4 GHz (8 Gb/s). The devices remained stable.
These probe cards allow accurate selection of good devices, facilitate modeling
(wafer device to PCM provides a broader selection of data, includes low gain
‘failures’ in the model and eliminates the need to track individual die identity
through to package level. Both cards incorporate edge
sensors.
MEMBRANE
REPLACEMNT CORE

10. MODEL
8 wafers of varying ‘quality were used in the model ranging from high yield to little or even no yield, ‘dead’ sites
were filtered out of the data. Sites were classified as dead if they exhibited no gain (due to mechanical faults). The
model was developed. A correlation coefficient of 90% was obtained with the model. The correlation coefficient of
the model is higher than any one PCM parameter to RF Device prediction, as shown in the following chart
.
Notice that the predicted gain (resulting from all of the variables) has a stringer correlation than any one of the
variables taken alone.
DEPLOYMENT
The model coefficients were inserted into an STM
language batch script and used to generate a summary PCM data
report. Data for that wafer in unloaded and run through the model algorithm. The output of the algorithm is the
predicted RF device gain for each PCM site using the 10 PCM parameters chosen for the model. A user calls the
program and enters a wafer number and the script generates a quality factor, this is the percentage of PCM sites that
have predicted gain that falls within the spec limits for the device, wafer RF gain contour map, PCM contour maps.
In addition the percentage of sites that pass PCM limits are also printed for each PCM spec limit both exclusively
and inclusively.
OUTPUT REPORT for each wafer with predicted device gain and yield.
Page 2 including a 3D plot of the predicted device paramter (highest pareto contributor to yield loss)
CORRELATION from Excel
vp1_50 vp10_50 subvth gm1_50 gm10_50 gm50_50 rch_50 nivdp gmextr_50 rout_50 gain predicted gain
vp1_50 100.00%
vp10_50 94.59% 100.00%
subvth 73.52% 47.53% 100.00%
gm1_50 47.99% 18.96% 90.48% 100.00%
gm10_50 73.74% 50.17% 95.12% 84.37% 100.00%
gm50_50 83.88% 71.92% 77.17% 54.30% 86.16% 100.00%
rch_50 58.06% 69.72% 11.76% -3.01% 7.87% 36.48% 100.00%
nivdp 0.92% 6.89% -11.90% -20.85% -28.99% -34.93% 11.59% 100.00%
gmextr_50 64.16% 49.20% 71.17% 57.67% 82.93% 84.41% 3.27% -44.09% 100.00%
rout_50 65.59% 50.70% 71.90% 57.76% 79.48% 76.80% 7.49% -30.60% 72.52% 100.00%
gain 74.22% 58.73% 78.53% 65.42% 84.34% 77.70% 10.98% -14.99% 78.75% 76.03% 100.00%
predicted gain 82.36% 65.17% 87.14% 72.60% 93.59% 86.22% 12.18% -16.64% 87.38% 84.37% 90.12% 100.00%

11. RESULTS:
The model has been used for wafers not included in the original model and has been working well. Some of the
parameters have been outside of the experience of the model. The model has performed well both in extrapolation
and interpolation. The accuracy however, can still can be improved by incorporating new data that is outside of the
past experience.

12. Here two models were created; one algebraic and one neural network and the results
compared.
Figure 1
Model: Predicted vs Actual Device Gain
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Data Line Number
GainindB
Neural Network
Excel Predict
Actual Gain
The graph in figure 1 plots the actual performance versus the predicted performance for both the
algebraic model created in excel and the neural network model. Data from subsequent runs was
used. This is not the modeled data. Note that the neural network data averaged out noise better
than the algebraic model.
Noise in dependant variable:
Several things have been learned subsequent to this which point out the need to understand the
data and the system. This device was found to be very sensitive to temperature. Temperature of
the wafer, even though on a controlled temperature chuck at 30 degrees C varied with room
temperature. Room temperature varied widely. This is due to the poor thermal conductivity of
GaAs. The top surface presents a large thermal face to the ambient room air, the back of the
wafer to the chuck. Thermal gradients therefore developed over the thickness of the wafer (12 mil)
causing a variation in temperature of the active area. The limiting amplifier gain is measured in the
open loop state (minimum input, no feedback, therefore maximum sensitivity to transistor
parameters) . A thermostream was later added to control the temperature of the air above the
wafer and of the probes, to match the chuck temperature. Long term traceability of wafer
standards kept a +/- .03 dB long term tracability to maximize wafer and package yield.

13. An additional error vector was found in a phenomenon similar to backgating, but not backgating.
Setting a negative voltage on the chuck would pull up gain (rather than decrease it as in
backgating) by as much as 4 or 5 dB. This usually occurred on devices which exhibited low gain to
start with (but not exclusively). I assume that the negative voltage was sweeping out trapped
charges in the channel of the FET’s, thus increasing the gain of the devices. This appeared to be
a random process defect that ranged from non-existent to severe and was dependant on location
of the device on the wafer. One could assume that PCM data would contain the same degradation
and still correlate to the device data. That would be incorrect in this case.
The PCM data was measured with the industry standard of +2.5 volt drain to source voltage.
However the device was biased with negative voltage. Thus the FET channel saw a negative
chuck (at 0 volts) with respect to the positive channel during PCM testing. In this configuration the
trapped charge carriers are swept out of the junction and the FET is enhanced. Thus the PCM
measurements were made with the test FET in an enhanced state.
The device is powered up with a negative voltage (chuck at 0 volts), the chuck appears positive to
the channel. In this state the FET does not have the trapped charges swept out of the channel and
the transistors are operating in a degraded state.
The effect of this is to add noise to the correlation. The important considerations are:
1) Averaging out the noise and assigning error bars to the prediction.
2) Ultimately, the goal is to eliminate the errors themselves.
A secondary form of modeling involves modeling the foundry. In this instance, a correlated PCM
parameter is modeled with respect to related parameters. The goal of this model is to see if the
process is behaving differently. While Control charts check for individual parameter centering, this
model would check for how related parameters vary with respect to each other. An example is Gm
10ma/mm predicted by Gm 20 ma/mm, Idss. The output would be represented on a bulls-eye plot
as deviation of the actual parameter form the predicted parameter (predicted from the related
parameters)
Summary:
Model can de developed to predict health of wafer and robustness error bars may be included to
include uncertainty in the prediction.
‘Human analysis is typically limited to looking at one independent variable versus one dependant
variable. O good analyst can visualize two independent variables interacting with one dependant
variable. Higher order visualizations are a problem however. Three independant variables
interacting with a fourth dependant variable requires a four dimensional plot. There have been
attempts at using color and even hypecube representations. Things get progressively worse
beyond 4 dimesional analysis. There are some difficulties with this in a three dimensional
existence.
A model however, has no such limitation and can deal with very high order dimensional anaylsis.
The accuracy of the model will be a function of:
1) The quality and type of the PCM measurements used.
3) The quality of the RF device probing.
4) The data selection criteria.
5) Understanding of the device, the PCM measurements and the modelling methodology.

14. Sensitivity analysis:
A further deployment after the model has been created is a sensitivity analysis that moves
parameters with respect to each other and measures the effect on the modeled output parameter.
Some modeling packages do include this feature, for those that do not, the effect can be scripted
or embedded in a GUI front end.
Additional monitoring:
Foundry can be monitored with control charts (check for design/process centering)
Foundry process can be checked for systemic variation by measuring deviation of a PCM
parameter from the predicted PCM parameter, to look for second order relationship changes in the
PCM data.
REFERENCES
Special thanks to Dave Harrison (AT&T GaAs Marketing Manager for Wide Area Network Circuits) for his help and advice in
preparing this paper. Jans Ransijn, AT&T GaAs designer of the LG1605 limiting amp. Jeff Williams at Cascade microtech for
characterizing the GaAs calibration standard I developed. Steve Smith at Cascade who worked with me to develop the high
speed membrane probe card. Gregg Bole at GGB Industries who worked with me to develop the high speed probe card for the
reduced pad frame version of the limiting amp. Eric King formerly with Neural Ware for collaboration on the concept of
deploying a neural network to model III/IV electrical performance.