cvlsnowdenokay47

https://www.linkedin.com/in/laird-snowden-11657015
I LED TH E BR IN G U P TE A M (O F SC I EN TI S TS A N D PR O C ES S EN GIN E ER S A T A T& T A N D TR I-Q U IN T.. S EE D R .
BR O P H Y A N D D A V E HA R R ISO N O N M Y LI N K ED IN R EC O M M EN D A TI O N ) O F O U R GAA S FA B A T TR I- Q U IN T
W I TH F IR S T LO T SU C C ES S IN J U S T 9 0 D A Y S. FAB: $1B
EX TEN SI V E D EV IC E N P I BR IN G U P EX P ER I EN C E A T S I LIC O N LA B S FR O M P LA N N IN G TO FU LL H I G H V O L-
U M E O FF S HO R E PR O D U C TI O N A S TE A M LEA D .
EX P ER IEN C ED A T BO TH A T& T A N D SI LI C O N LA B S IN C M O S , BIC M O S, SI G E, BE L L C O R E S P EC , M I L SP EC
TE S TIN G , Q U A LI TY A N D FA A N D PR O D U C T P LA N N IN G , A N D M A N U FA C TU R IN G P LA N N IN G D EV E LO PM EN T
A N D D E P LO Y M E N T TO FU L L H I G H V O LU M E PR O D U C TIO N IN A LL A SP EC TS.
BU SIN ES S EX PER IE N C E: I S TU D IED O U R E B TID A LO S SE S A N D F IX E D TH E GIA N T PR O FI T HO LE A S W E LL A S
SM A LLER O N ES, O U R S BU W EN T FR O M TH E LO S S TO M O S T PR O FI TA B LE A T 5 0 % R E TU R N O N $ 5 0 0 M GR O S S
SA LES FO R TH E G A A S S BU . $250M PROFIT A S A R E SU LT O F M Y A C TIV I TY
BUT STILL TRY
FOR WHO CAN SAY
WHAT IS POSSIBLE
M. FARRADAY
...Science Building at Ursinus College.(Pfahler Hall).
I like to fix broken divisions, processes and devices, Build new things
C U R R I C U L U M V I T A E
LAIRD REESE SNOWDEN
Phone: (512) 312-4891
E-mail: larsnow1@aol.com
AEL

INTRODUCTION:
Exceptional Business oriented Engineering Professional with an effective record of achieve-
ment in Business Turn Around and new technology bring up by implementing optimal solutions
for complex engineering projects in concept, prototype, design, redesign, quality, and testing.
Consistently providing thought leadership in the creation, implementation, and delivery of game
changing solutions proven to achieve or bolster product quality and profit. Adept at identifying
and building solutions that reduce product lead times, warranty exposure, and eliminate field
performance issues. Tenacious when forging long-term relationships with external and internal
business partners that achieve sustainable and scalable results.
Business Skills:
BU turna round, Product Development, Product Management, Cross-functional Team Lead-
ership, Strategy, Product Market Analysis, Management, Competitive Analysis, Start-
ups, Strategic Partnerships, Go-to-market Strategy, Manufacturing Strategy, Yield Opti-
mization, Profit Optimization, Manufacturing strategy, Manufacturing bring up, Testing,
Process Improvement, Risk Mitigation, Critical Product Definition
Engineering Skills Highlights:
NPI Testing & Validation Product Design Semiconductor Fab bring up, GaAs SARGIC,
ERGIC, CVD, CMOS, BiCMOS, SiGe Statistical Analysis, Data modelling , Relational data
base construction, Yield optimization, Device FA, Process FA, RnS Production Test auto-
mation, Test Executive, Lab Setup, ATE device test development, ATE Tester Develop-
ment: hybridization, DOE, Advanced data analytics, process/device centering, qualifica-
tion testing to Mil Spec, Bell Core, JEDEC standards, Customer Application Engineering,
Test Programming, Test Tool programming, Statistical analysis programming, Test/
network data bring up.
MY TEAM: Building the
worlds first ATE/SONET IP
ATE tester.
C U R R I C U L U M V I T A E
L A I R D R E E S E S N O W D E N
.
Phone: (512) 312-4891
184 Avenida Tejas
Kyle Texas, 78640
L A I R D R E E SE
AEL

WHEN MY WIFE PASSED AWAY AT THE END OF 2012, I WAS UNDONE. I TOOK
A SABBATICAL TO PUT MYSELF BACK TOGETHER AGAIN. DURING THIS TIME, I
STUDIED THEOLOGY, POETRY, LITERATURE.
I BUILT MY OWN LIBRARY OF OLD AND ANCIENT BOOKS, PREFERRING THE
WISDOM OF PAST AGES TO THE CLANGING TIN OF POST MODERN LIBERAL
ARTS
MOST OF THE BOOKS I COULD AFFORD WERE IN PIECES, BEING OVER A HUN-
DRED YEARS OLD, SO I YAUGHT MYSELF BOOK BINDING TO REPAIR AND CON-
SERVE AND FULLY RESTORE THEM, SO THAT I COULD READ THEM.
I ALSO CONSERVED OLD FILMS, MACHINE AND RECORDS AND BUILT SOUND
SYSTEMS TO RESTORE FULLY THE SOUND FIDELITY OF OLD RECORDS TO
THAT OF A LIVE PERFORMANCE VENUE .
LAST YEAR I TOOK UP RESTORING ANTIQUE CLOCKS, TAUGHT MYSELF HOW TO FIX THEM AND
MAKE THEM MORE BEAUTIFUL THAN WHEN THEY WERE NEW.
I AM BUILDING A PROFESSOR JULES VERNE ORRARY WHICIH I HAVE DESIGNED.
I ALSO BUILT A PLANETARIUM FOR MY BEDROOM
I HAVE STUDIED IOT, MCU CONTROLLERS, INTERFACECES.. THESE ARE RATHER ELEMENTARY
AND EASY PROJECTS SIMILAR TO MY EARLY WORK AND FUN.
I HAVE DEVELOPED TO DEBATING SKILLS ON FACEBOOK, TO EVEN THE MOIST OBTUSE AND
INTRANSIGENT PEOPLE,
NOW BREAK TIME IS OVER, TIME TO HET BACK TO WORK.
I MUST ACQUIRE FUNDS TO BUILD A MISSION FOR THE HOMELESS.
RESEARCH: DURING MY SABBATICAL 2013 TO PRESENT
Human Audio Cortex: mapping data processing functionality | Brain function | Human Visual Cortex: map-
ping data processing functionality | Artificial Muscle actuators Cloud Computing | extemporaneous Music
Composition | Arduino development | Solar Energy | Quantum Mechanics | Astro Physics, | architecture
chapel design | curating old film | restoring antique clocks, curating and reading old books and manuscripts
| audio sound field restoration | global warming | Built library of Antique books for study : Theology, Po-
etry, Literature
.
S A B B A T I C A L
Phone: (512) 312-4891
2013 to pre-
sent
I restore them , repair them
and add figural garniture
The Grand Sonnerie also
known as a “quarter Repeater”
is one of the most complex
mechanisims, it, like all if
clocks I can afford, arrived
broken, and I disassembled
and repaired the mechanism.
The clock in fornt is a Willard
I taught myself clock
making in less than a
month and my collection
is now completed in a
year.
This has been very thera-
peutic, and I love hearing
the chimes, which I have
also made more beautiful.
I just made a beautiful
Sonora 9 bell movement I
installed in an empty wall
case I bought… it is a fun
hobby

.
S A B B A T I C A L
2013 to pre-
sent
Via Dolorosa
Book I wrote
My own custom binding.
Chapel I designed, I obtained stanind glass from churches being turn
down… I wanted to create emblems of the Christian faith on the
order of a first century church
It has been built and is now a cloister
I was fortunate to drive the design of this project .
There are many emblematic details in the design.

.
S A B B A T I C A L
2013 to pre-
sent
One more thing I will cite.
I purchased a Yamaha Clavinova CVP digital piano (used of course)
My wife wanted me to teach her to play. I had two years of lessons
when I was a teen ager, have not played since.
She could not however, due to the neuropathy.
So I forgot about it. After my wife had passed… I did save her spiritu-
ally, I failed to save her from the disease that took her.
I decided to buy a piano and decided I might feel better if I played a bit
after she had passed.
I found, for whatever odd reason, I could compose classical music in
real time, with my eyes closed (I can hear the next notes that need to be
played more clearly that way), and my fingers still have keyboard mem-
ory.
And that has helped, it a great blessing.
Here is an early example, #35. I may improve it if I worked on it, but
this is sit down and then once and done, straight through.
And this has also helped me a great deal, top put my soul back together
again, after my wife had been torn away.
And if you do not believe it, well, that is not my problem.
lrs_composition_35_wmf.wmv
This is for my wife Sue, she loved
the deserted beach at winter.
Double click to play
Magic Lantern I converted to
electric
Curating old film and film pro-
jectors (1927 first auto thread-
ing projector)
My two feral kittens I found
outside and domesticated, my
little buddies are good for my
soul.
An Edison phonograph I re-
stored.

.
S A B B A T I C A L
2013 to pre-
sent
AUDIO SOUND FIELED RESTORATION .
I have designed and built audio systems to re create the live sound field
lost in recording.
I have a system I built for LP records, Tape and CD
Another system for 78 lps
Another system for my home theater and DAT Tape.
Each one different, more for experimentation
(add pictures)
Magic Lantern I converted to
electric
Curating old film and film pro-
jectors (1927 first auto thread-
ing projector)
My two feral kittens I found
outside and domesticated, my
little buddies are good for my
soul.

One day, we had every Production/Test engineers worst nightmare. Good parts were failing
catastrophically on Quality Assurance lot sampling re-test. This is where a lot is pulled out of
productions after all the steps are completed and retested. This means we may be shipping
bad parts to the customer and worse, parts with latent damage that could fail in the field
Detecting root cause is a detective job.
Die Crack ?
Another Qual lot was run, and the same result. In fact re running the same lot continuously
produced failures. I need not say that we should be able to retest the same part all day long
and never cause it to fail, otherwise, we are creating latent damage.
The parts were X-ray'd and some cracks were seen on the die and that was assigned the prob-
able cause.
I looked at the pictures and had SEM's run and said "No, they do not propagate past the seal
ring. I do not think this is the cause, they are not intruding into the ESD structure. By the
way, the failure was a catastrophic short along with loss of functionality.
ESD Damage, Not Die cracks
I ran the bad pin on a curve tracer and identified a short that looked to me like ESD damage,
however a die crack intruding into the ESD circuitry under the pad could look like ESD dam-
age. But i noticed these failures only occurred on the outer ring of balls.
I said, "I think it is ESD damage". I was told no, we have never had a problem like that.
I gathered data and did some detective work:
1. the package was redesigned.
2. the handler kit had to also be re designed
3. the handler input/output trays were a new vendor.
The first thing i did was look at the failed part under a microscope. I looked at the balls and
noticed:
1. they were close to the edge of the package
2. they had a slight lean to them, towards one side.
i checked with the package engineer and reran the parts through the visual inspection machine
and they passed and were confirmed to be in spec.
I measured the ESD field being generated on the endeffector of the handler by undocking
it and running and cycling it. I saw the voltage rise to 3000 Volts !
No damage on insertion, all pins contact socket contact at once, so MM ESD discharge is dis-
tributed. However, on insertion in outgoing metal tray, one pin may lean too far or by being
positioned on the end effector a bit crooked, one pin is presumed to contact sloped metal tray
wall (sloped to align part) All Machine Model ESD voltage is discharged through one pin
causing extensive damage.
Corrective Action:
Purchased portable balanced blower/ionizer, ducted to test chamber: Voltage immediately
dropped to less than 1 volt, problem ceased
Order internal test chamber ionizers.
PROBLEM FIXED.
,
L I N E D O W N , M Y S T E R Y
P R O B L E M
L A I R D R E E S E S N O W D E N : S I L I C O N
Ctr_click:Quality / Productivity
Restoration: Tasked with resolv-
ing an unknown manufacturing
fault that crippled production.
Investigated and identified root
cause was lack of propagation
past the seal ring. Examined ma-
terial specifications for root cause
of ESD damage levels, ordered
appropriate parts, and designed a
temporary solution to prevent
operational interruption. Con-
ceived, created, tested, and vali-
dated an alternate strategy. Once
device was validated, led modifi-
cations and testing. Within 30
days, production was restored,
increasing quality and cus-
tomer satisfaction.
2003 to
2013

Our RDL phase noise jitter measurement instruments were obsolete and at their end of
life, failing frequently, causing line down problems.
Since we manufactured sub picoseconf devices, we wanted to verify performance, there
are few options in that area of performance
I spoke to Agilent, they brought their instrument and I interfaced to our ATE and put a
part in. The E5052 failed miserably. Reporting jitter far too high.
I showed our Agilent rep that the instrument used a brick wall filter rather than the OC48
and OC192 corner filters.
I told our rep that all Agilent needed was to add a digital filter, I outlined the flow inside
the instrument, and asked him to either give me the internal software so I could imple-
ment is or have their SW people add it. I told him I would buy his instruments to replace
all of our aging RDL’s if this feature were added. I also told him he could offer it to all his
customers and that I therefore would not pay for it.
I created the SONET filter coefficients in excel for loading into the firmware, so I can up-
date them as I need.
So, I now have the software to run OC48 and OC192 jitter tests. It uses the captured
phase noise plot so it only runs one sweep to return
Brick wall jitter
OC48 Jitter
OC192 Jitter
The new noise floor is now 7 femto seconds with the digital filter.
And best of all, measure time reduced for over a second with the old RDL’s to less than
300 mS and lower noise floor !
Verified with Wenzel Osc with 13 fS jitter… measured 13.2 fS ! Verified low noise floor
with digital filter.
C R E A T E D N E W M E T H O D F O R
J I T T E R P H A S E N O I S E A T E
M E A S U R E M E N T S
Our old Phase noise RDL test instru-
ments were at their end of life, Ex-
cessive down time in testing. Design
engineers proposed SA technique,
were slow and costly. Commis-
sioned to increase testing perform-
ance, reduce cycle times, and reli-
ability. Built the strategy and led
execution to investigate capabilities
and options and partnered and ne-
gotiated modifications with Agilent to
extend performance. Once design
methods were negotiated, signed
contract for improvements. Within 30
days, eliminated downtime, short-
ened testing, increased output, and
reduced cost. Reduced test time
goal from 2 seconds to 300 milli-
seconds. This established the
new global standard for testing
and performance
2003 to
2013

.As an NPI STAFF Engineer for our first Si5300 Any Rate clock generator, I saw that we were
using Frequency counters which had a 1 year calibration cycle to set the final frequency.
I immediately pointed out that if just one counter failed its yearly calibration verification, then
an entire years with of product could be subject to recall and there would be some very unfor-
tuitous customer notifications, with the worst possible nightmare of field recalls.
I researched and deployed a PRIMARY NIST TIMING REFERENCE. This needs is not a
secondary standard. It is an operational PRIMARY STANDARD.
The rubidium oscillator which is an gas cell oscillator, maintains the exact frequency during
GPS denied intervals. The life of the gas cell is approximately ten years. As the gas cell ages,
the GPS disciplines the Rubidium oscillator to correct the Allen Variance aging of the Rubid-
ium clock.
The GPS signal has poor short term accuracy due to multi-path timing errors of the signals,
however its long term accuracy is that of a Cesium Beam oscillator, which is maintained at
GPS ground station uplinks.
The system also has built in alarms for multiple failure modes, and so it gives failure warning
and can take declare a crowbar shutdown on error in real time, requiring an equipment substi-
tution (you will have a spare for your test floor… right ?)
The system also uses a 10 MHz signal distribution amplifier for each test set timing reference.
I deployed this at Silicon Labs on shore for test bring up and offshore for full and safe produc-
tion testing .
,
G P S / R U B I D I U M P R I M A R Y N I S T
T I M E I N R E F E R E N C E
Frequency outputs with counters
were calibrated once a year and
faulty programming errors had the
potential to go undiscovered for up
to 12 months, causing all production
to be subject to recall. Over the first
30 days, researched, purchased,
and deployed a real-time primary
NIST timing reference and used a
rubidium clock paired with a GPS for
quality and accuracy. By the 90th
day, achieved guaranteed quality
parts risk mitigation avoiding
recalls and establishing higher
benchmarks for quality
2003 to
2013

.As a Mixed Signal Staff Test and Production Engineer., I needed a way to quickly create ATE
tester specific test patterns . Typically, on our advanced parts, these must be hundreds of thou-
sands of lines, with multiple start and exit vectors, embedded analog test micro code, multi site
device NVM configuration and verification digital content, pass/fail digital compares and
HRAM transfer in different communication protocols.
Requirements I addressed with my macro:
1. Easy to edit
2. 2. error free compilation
3. Well commented during ATE debug
4. Encapsulated and summarized for Design feedback of failures and documentation
5. Archival for future reference and updates
.
I wrote and excel macro which reads a spread sheet of simple opcode—operand commands
and creates perfect commented test patterns.
This save huge amounts of test time development and prevents errors. It is maintainable.
This allowed me to bring up highly complex device test, configure and optimize testing for
highly complex devices that are centered to the process to create perfect test specs. These
devices also have multiple configurations, so must have complex patterns. Test time must be
less that 2 seconds, so efficiency is important.
I found broken HRAM hardware in the J750, analyzed the failure and wrote a work around
option in my pattern generator macro
This allows the tester to transfer all of the data from digital pin hardware to software
HRAM array for ALL SITES, for ALL BYTES recorder in the same time it takes to transfer
one bit resulting in a huge test time savings. Wrote matching J750 read function to work
with the patterns
Created pattern structures to optimize pattern execution for setting different digital con-
tent in multi site devices.
M I X E D S I G N A L T E S T P A T T E R N
M A C R O O P C O D E / O P E R A N D T E S T
Ctrl_click:Software Design
Wrote mixed signal digital pat-
tern generator for all proto-
cols, I2C, SPI, Manchester etc,
with microcode
Dr. Sundar Chetlur
Director of Wafer Technology at
Allegro MicroSystems, LLC
Laird and I worked together on a
number of product yield improve-
ment activities at Silicon Labs. The
most memorable were improving
poly-fuse programming to avoid
"disturbing" adjacent bits and fixing
Fmin/Fmax issues on timing prod-
ucts. I found Laird to be prompt,
knowledgeable and extremenly tena-
cious in solving tough problems.
April 20, 2015, Sundar worked with
Laird at Silicon Labor
2003 to
2013

.COMPLEX PARTS WITH MULTIPLE CONFIGURATIONS require many
different patterns . I do not modify patterns on the fly because this is a much
slower process than running pre compiled fixed patterns, with multiple entry
and exit vectors.
The Si500 package test is highly complex, to solve this, I wrote on test pro-
gram and made it configurable,. I read the device type from the customer data-
base, using the travelling lot number. This then downloads key information
that configure what tests to run, what NVM bits to set, how o test and bin
parts.
The program identifies programmed pr partially programmed parts (pin contact
fail;)n for automatic retest, it then verifies device performance on programmed
parts and if partially programmed, verifies partial programming then continues
to program part (if verification passes)
The program also has many engineering pages that can be turned on with a
simple key on the page that extracts and plots in process engineering informa-
tion such as reading and plotting internal registers for design/fail issue check-
ing.
In production mode, engineering page and switches are denied to save interro-
gation time to meet 2 second test time for fully thermally compensated any rate
oscillator !
S E L F C O N F I G U R I N G T E S T
E X E C U T I V E
Ctrl_click:Test Executive: Wrote
test executive that automatically
configures the test and device
configuration software to produce
custom programmed parts and
test them from the customer order
database.
2003 to
2013

.Profit loss due to technical errors caused AT&T to consider outsourcing. Performed production cost
analysis, identified contributing factors, devised, and implemented a recovery strategy. Wrote 1MM lines
of code and deployed in production. This eliminated production set hang-ups, improved throughput,
opened test operations to all operators, and reduced errors to zero.
When I took over wafer probe for AT&T fiber optic chipset, we had custom test execu-
tive and it was very hard and non intuitive to use, it hung up frequently and was
poorly written.
I decided the first thing i needed to do was rewrite both the test software and the un-
derlying test executive that controlled the low level and high level
probers , instruments, data collection and operator interface, about a million lines. I
completed this in several months. I completely reworked the operator interface, so
that the only thing they entered from the lot carrier was the lot number and device
code. The computer now setup the prober automatically and took over to even load
the correct test program and start operating. All of the operators were now able to
operator the probe testers and there were no more hang ups thus increasing through-
put, reducing scrap and down time that had been caused by damaged probe cards and
scrap reduction due to damaged wafers and ease of operation was vastly improved, the
test executive loaded the correct test program and filled in all of the arcane control
parameters automatically. I added additional cores to the software, such as adding a
full statistical analysis and auto report printing function, which i wrote as well, in
HPB.
I continued with new device test bring up, which was now very easy, just an add on to
the root test executive, which was the same for all devices and robust. It only required
two or three days for me to bring up new Analog RF Testing for new products now,
using my new software, so development time was also shortened, full data reports
were generated for each wafer and printed on the shop printer automatically.
W R I T E T E S T E X E C U T I V E : F I X
E X C E S S I V E L I N E D O W N
P R O B L E M
L A I R D R E E S E S N O W D E N : A T & T
Ctrl_click:MANUFACTURING
EFFICIENCY Restoration: Profit
loss due to line down problems .
Performed production cost analy-
sis, identified contributing factors,
devised, and implemented a re-
covery strategy. Wrote 1MM lines
of code and deployed in produc-
tion. This eliminated production
set hang-ups, improved through-
put, opened test operations to all
operators, and reduced errors to
zero
Dr. Hans Ransijn
Analog Design Engineer at Multiphy
Laird and I worked together at
AT&T Bell Labs (later Lucent and
Agere) in the 90's on multi-Gb/s
telecom ICs that were state-of-the-
art at the time and that were manu-
factured in high-performance but
relatively immature III-V technolo-
gies.
Laird developed high speed wafer
tests for these ICs, but didn't just
stop at circuit characterization. Since
we were pushing the limits of the
level of integration for these III-V
processes, maintaining yield was
critical. Laird was instrumental in
developing statistical techniques that
allowed accurate performance yield
predictions.
I enjoyed working with Laird. He is
a thorough professional with an easy
demeanor, is un-assuming and a
tireless worker. I highly recommend
him for any engineering job that
includes test hardware and software
development, characterization, mod-
eling, data analysis and the like.
April 21, 2015, Hans worked
directly with Laird at Bell Labs
AT&T/Lucent Technologies
1988 to
2003

Our SBU was the least profitable at AT&T . We were always called “That rat Hole” at the
company SBU reviews, but we were critical, strategic to AT&T infrastructure making a mil-
lion dollars a second on its longlines data and voice network.
After divestiture, however, outsourcing came into being… could anyone duplicate our products,
not likely, however, that Is no guarantee the GaAs SBU would not be scrapped, with a so called
lifetime build on the shelf.
I knew that I could fix this. I was at the nexus of Wafer Process, Wafer Device probe and pack-
age test. The first thing I did was to print out production data, process data everyday and study
it. My Bell Labs nick name was”Treeslayer”… better than some others.
When I saw what I needed, I created a relational engineering database and the crons to load
them from the tester flat files, which I also create in my test executive.
I made careful discrete to continuous data models (technically impossible.. But not if you know
what you are doing, such as 1 of N transforms), I used this to reset the wafer probe test limits
and also analyze the validity of the wafer tests. I reset the wafer limits with this information and
performed post binning to see how the yield map changed. I found the maps changed from
scatter shot to neat images.. Ghosts and smiles actually. Then I had added test fets and sheet
rho structures to the primary sites and used them to make 3D photographic images of the proc-
ess data. Slicing the critical parameters revealed the exact yield patterns, identifying the proc-
ess targets.
Next I wanted to model the process data to predict package performance, this was a model
from process to package parametric data. I needed to aggregate the PCM and surrounding
device sites to create data sets for modeling. I did this by creating virtual clown numbers, these
can be written into spare NVM space.
Here I was told that such models were impossible, there is too much intra and inter wafer lot
variation for modeling, or data transformation. The problem is non orthogonal data with infor-
mation in the tails. I found a new method, never used in semiconductors before at that time..
Neural Networks. I studied this at the Gordian Institute and Neural Ware and then created my
models, which predicted final package yield based on parametric predictions from process data,
so that I could know the expected wafer yield before it was tested.
AT&T Bell Labs had attempted to create models from uncorrelated data with continual failure eroding
profits. Internal research revealed a ctrl_click:methodology that could handle all of the constraints. Had to
develop a photographic map technique of PCM wafer process data in 3D imaging to understand the yield
patterns. These efforts resulted in creating an understanding of the process, which improved yield
and throughput and resulted in SBU restoring profitability and becoming the most profitable divi-
sion of AT&T Bell Labs microelectronics GaAs SBU with $250M in profits. Ctrl_click:Wrote a pub-
lished IEEE paper on the method
S B U T U R N A R O U N D
Ctrl_click:SBU Turnaround | from
loss to $250M profit on $500M
sales: Yield & Throughput Im-
provement: .
20,000 stock options
awarded for my work and
promotion to Senior MTS.
David Harrison: GM GaAs SBU
Visionary Entrepreneur
Laird worked in the Gallium Arsenide
business unit at AT&T Microelectron-
ics and Lucent. He created models of
the GaAs process data to predict de-
vice yield using Neural Network tech-
niques to capture data in the distribu-
tion tails of high dimensionality non
orthogonal data. He deployed scripts
that printed out yield estimates for
each lot. This was used to build our
inventory during the down time when
our entire GaAs IC fab line was trans-
ferred from AT&T Reading, PA to
TriQuint Semiconductor, Oregon. . He
built sufficient inventory to cover the
production outage. Laird coordinated
the weekly meetings for process bring
up between AT&T Reading and Tri-
Quint to set process targets derived
from his data analysis and models.
First wafer lot from TriQuint was a
success.
Laird also coordinated the world
first Telecommunication Big Iron
Test Set with LTX on an LTX
Fusion HF tester and hit the pro-
duction test time goal of 4 and 8
seconds for the 2.488 GB/s Trans-
ceivers.
Hebbian Self organizing NW
1988 to
2003

.ctrl_click:Hybrid ATE
I defined and lead this project to build the
worlds first ATE/Sonet telecom tester for
the longlines transceiver project.
This met the full test spec and reduced test
time to 4 seconds well below the Rack and
Stack test time of 30 minutes !
Up to this time there was no ATE capable
of running the full test suite.
I developed the RF methodology, new
hardware, including a low jitter atomic clock
reference, a new phase noise jitter calcula-
tion, digital buffer by pass for jitter, methods
for jitter generation and jitter tolerance and
BERT testing.
W O R L D F I R S T A T E / H Y B R I D
T E S T E R
Cttrl_click:Testing: : Our C level
manager asked me if I could
build a tester to test our new
transceiver chip set in high
volume. I said yes and pro-
posed building a Hybrid ATE/
Telecom tester with LTX, other-
wise, it was not possibleLTX to
build a ctrl_click:Hybrid ATE on
their Fusion HF platform in 15% of
the usual testing time. With a
$3.2M budget, within a year, de-
signed an intermediate device
personality board, created test
methods, and developed handler
and manual testing interface hard-
ware. This was accomplished
within cost and throughput
goals, creating a new standard
for telecommunication testing.
Note: I worked with Brent on
bringing up testing on the
new Hybrid test platform.
Brent Schusheim
Click to drag this recommendation
Electrical/Electronic Manufactur-
ing Professional
I worked with Laird on high speed
data communications semiconduc-
tors at Lucent Technologies. Laird
was knowledgeable of these leading
edge devices and contributed signifi-
cantly to the production test solu-
tions. He was easy to work with and
an outstanding test scientist.
Brent Schusheim
May 22, 2015, Brent was with an-
other company when working
with Laird at Bell Labs AT&T/
Lucent Technologies
1988 to
2003

.Tasked by GM and Chief Scientist with leading
Technical methodology to Bring up our $1B
fab, which we transferred from AT&T Reading
PA. to Tri-Quint OR. This is one of the world’s
most complex Semiconductor fab processes
(SARGIC HEMPT EPI III-V GaAs
semiconductor). Our Wireless SBU tried for one
year and 9 months and failed. I was tasked to
take over the transfer, Over the course of 90
days, devised the strategy and led implementa-
tion by defining goals, roles, and tasks with
metrics to chief scientists and validated results.
Achieved a new first in wafer yield at 98 per-
cent. This met customer reliability require-
ments and AT&T continued to earn $1M per
second. Awarded spot stock options and
cash awards
$ 1 B S A R G I C H E M T E P I F A B
B R I N G U P
Restoration; Lead team for
$1B semiconductor fab
bring up: .
Restoration; Lead team for
$1B semiconductor fab
bring up: .
Dr. Martin Brophy
GaAs Process, Reliability, Product
and Test Development Engineer at
Avago Technologies
I worked closely with Laird and
the team at AT&T Reading in the
early 1990's doing a process trans-
fer of 3 HEMT processes for 2.5
Gbps SONET systems from their
smaller fab to TriQuint Orgeon's
big GaAs fab. It was a major ef-
fort for us in Oregon because it
was the first epi GaAs process
brought up in our fab. As you
might expect from AT&T and
Bell Labs, the technical interac-
tions were excellent and great
learning experiences for me. Laird
played a big role in getting that
project completed with excellent
first pass success. He has consis-
tently demonstrated knowledge
both broad and deep in many
areas of GaAs processing, reliabil-
ity, and test for both optoelec-
tronic and electronic applications.
He would bring great and broad-
based experience and knowledge
to whomever is lucky enough to
hire him and I recommend him
highly.
1988 to
2003

This is my FA LAB I put together
and used at AT&T for internal RF
die probing and microscopic in-
spection, curve tracing etc on NPI
devices for both wafer and delided
parts.
That is a three color laser for cut-
ting through SiN cap or metal.
Our Electron Microscopes and X-ray machines were in the basement level, each had its
own operator.
My NIKON Microscope was to the left.
Namarski filters,
Confocal.
Photoresist filters
M Y F A L A B I O U T F I T T E D O N
T H E B E L L L A B S R & D L E V E L .
1988 to
2003
Dr. Hans Ransijn
Analog Design Engineer at Multiphy
Laird and I worked together at AT&T
Bell Labs (later Lucent and Agere) in
the 90's on multi-Gb/s telecom ICs that
were state-of-the-art at the time and
that were manufactured in high-
performance but relatively immature
III-V technologies.
Laird developed high speed wafer tests
for these ICs, but didn't just stop at
circuit characterization. Since we were
pushing the limits of the level of inte-
gration for these III-V processes, main-
taining yield was critical. Laird was
instrumental in developing statistical
techniques that allowed accurate per-
formance yield predictions.
I enjoyed working with Laird. He is a
thorough professional with an easy
demeanor, is un-assuming and a tire-
less worker. I highly recommend him
for any engineering job that includes
test hardware and software develop-
ment, characterization, modeling, data
analysis and the like.
April 21, 2015, Hans worked directly
with Laird at Bell Labs AT&T/Lucent
Technologies

.I was called to solve a spurious problem causing our new Defense Electronics module , a double mixer
converter, ten band with digitally selected bad settings, to fail final test. My spurious ID tester, which I
had just built identified an RF input spur coming out the output.
I found it was not a lossy transmission line as my boss had supposed.
I built an RF sniffer probe that worked at mid band microwave frequencies involved.
I found the problem was actually the third band LO frequency was leaking out of the first mixer (first
order fundamental leakage, normal for all mixers,). The signal then entered a wide band amplifier. I
reasoned than any nonlinearity would cause the LO3 and IF3 to mix and recreate the RF input. No am-
plifier is perfectly linear, sure enough a very small RF spur came out of the amplifier that was not at the
input. The spur then passed through a second digital filter and was in band, it passed through a second
image cancellation mixer and was in band and it passed through yet another filter to the output amplifier.
The odd thing was that the spur was in band all the way through. Amazingly the NRL (Naval Research
Lab) had specified a very narrow notch filter at the input to that intermediate amplifier where the spur
first appeared on the output.. And it was set the first mixer LO3 frequency ! SPOT ON. Those NRL folks
were sharp
I told my boss and he said NO, look for lossy transmission lines like I told you to do. I said I did and
they are not, he said look again. .
Finally I saw lab neighbor working with a ceramic puck, I said, cool what is that ? He said he was de-
signing a ceramic resonator. I asked him for the white paper, curious. I found I could use that to reflect
the LO3 right back the amplifier and prevent it from traveling through the module and getting amplified.
So I asked him to get me some samples at the LO3 frequency.
The day came ! I put the first one down on the amplifier output micro strip and tuned it as a resonant
cavity by turning the ecosorb metal RF ustrip cover upside down and spacing it with shims… AS SOON
AS I HIT THE LO3 frequency, the RF SPUR at the output dropped into the noise floor… SUCCESS.
I told me boss and asked him again who designed the amplifier, told him the filter was not working and
we needed to open the module and fix it.
HE TOLD ME THE FILTER WAS NOT THERE !.
I asked “WHY NOT?” He said Don T (head of electrodynamics at Lehigh and chief AEL scientist said it
was too hard to design would cause problems and was not needed. I said.. Well it really is needed and
there are no problems with my reflective filter.
Again I was scowled at and told to go back and design an absorptive filter.. I said NO, it is not needed,
the amplifier output is VSWR protected and it is a small signal .. My filter caused no out of band pertur-
bations and was used in final production.
I save d the company an additional $3M by using my strip cover and shim tuning, and wrote a manufac-
turing procedure to guarantee stability in the tail of an F-15 and I got to see it work in the gulf war when
all the SAM missiles were flying sideways.
R F C E R A M I C F I L T E R , F A O N
D O U B L E M I X E R C O N V E R T E R
L A I R D R E E S E S N O W D E N : A E L
Called upon to ctrl_click:restore
quality to an electronic warfare
module after 9 months of part
failures risked the loss of a signifi-
cant military contract and associ-
ated penalties. Investigation re-
vealed design issues was cause
of the out of spec test failure.
Designed new ceramic resonator
filter and created manufacturing
methods for tuning frequencies.
This saved $2MM in costs and the
products passed audits meeting
all contractual obligations. This
achievement prevented default
penalties and preserved reputa-
tion and right to bid on future
contracts.

My boss found an Access time tester and then decided to use a commodore 64 to exercise the memory functional test.
My Boss let me design the tester and build it, I was a junior engineer and I must say, he is a great guy. So i designed and
interface using memory mapped IO and Transmission gates that allowed me to program the logic levels and threshold
detection.
The Commodore lacked sufficient IO to run my board so i had to expand the IO. I designed thee expanded IO using Com-
modore Versatile Interface Driver chips. Problem was, they were proprietary and could not be purchased. Fortunately my
friend and former classmate worked at Commodore IC fab just down the road and agreed to meet me at the back door at
night with some "samples". Thus was born our tester. Well, it was a huge silver box with wide ribbon cables running every-
where, a GPIB adapter, an access time tester matrixed into the test socket and of r a commodore 64.
I found the test time was way to long, so i taught myself assembly language and programmed the memory sections in as-
sembler, and found out how to sub out to the assembly routines, which took test time from 30 minutes to 10 to 20 seconds.
I interfaced a matrix of sockets into a lab oven door so we could test at temperature. I hated cutting out the metal slots, cut
my hands up doing that, but I designed and built and programmed this thing from the ground up.
Well , the day came for the Military and the first source to inspect our tester. They looked at it and laughed us (me) to
scorn. THEY had a BIG ATE memory tester, VERY EXPENSIVE AND VERY IMPRESSIVE LOOKING, I wished I had got a
big impressive box to hide my little tester in, oh well, too late for that. There tester came from IBM and I think they
brought a contingent of IBM people with them, to add to the laughter. I had a pathetic little commodore, with wires stick-
ing out all over.
Fortunately, they let us test parts and ship them to the NRL who put them in SUBACS SYSTEMS with no returns.. EVER,
maybe one, they dropped in a solder bath and it blew up.
These multi chip modules were assembled from 100 percent tested die. I had 50 to 80 percent yield on 100 percent tested
die. I was told my yield should be 100 percent, i said: well, no... it is not. I was sure i was correct, because i had data to
prove it and had performed the verification of the failures, they (being the GM) had conjecture about the meaning of the
words "100 percent tested die" and no data. Nevertheless, i had to repeatedly exhaustively verify every failure for them,
since they had the big office and i had the little office at that time. We found a multi chip package tester that you put a
fluid in the stimulated the pins and the connected pads would flash... all good. Next i was told to verify the bad DIE, since
my tester must be bad, IBM had 100 percent yield at the tester you see. So i traced each fault to a shorted address or data
register or an open register by stepping through the test and re writing the software to do this. Yes, the memory locations
were bad… ABSOLUTELY, many times writing to one memory location simultaneously wrote to another memory location
or an entire row or column.
Finally the day came when the NRL sent 10 chips to us. It was
a blind test… these were definitely not ours
I was told to test them and report if i found any bad. I did, i found 5 bad, 5 good at room temperature. One the good ones
failed at test condition hot.
I was then told that 5 were indeed bad and 5 were good and the NRL wanted me to confirm it for them because our first
source, with the very big, expensive and fancy tester claimed they were good and passed retest, the NRL found they failed in
the system. I found they failed also. . I asked if the 5 were also tested at hot or just at room. I was told "just room" i told
them one of the good ones will fail at condition hot.
After that no one laughed anymore.
D E S I G N E D A N D B U I L T M Y O W N
M E M O R Y M A P P E D S U B A C S P R O D U C T I O N
H Y B R I D M E M O R Y T E S T E R .
Ctrl_click:Customized Testing /
Validation
Lack of capability for testing of com-
plex modules frustrated leadership.
Tasked to create a memory tester to
increase throughput, reduce rejects,
and eliminate returns. Interfaced an
access time tester and acquired
pass-fail test vectors, expanded test
procedures, and designed and built
hardware and software. Created
thermal test chamber and added
debug test routines, retest test flows
and validated. Delivered a superior
product while eliminating millions
in costs and demonstrating supe-
riority in blind tests against com-
petitors
Paul Kurland
Franchise Owner at Cruise Planners
Paul Kurland
I can remember the challenge Laird
and I had to come up with a way to
test a memory hybrid for the Ad-
vanced Light Weight Torpedo pro-
gram without having to buy a
sophistocated and expensive mem-
ory tester. With Laird's expertise,
and the help of a Commodore 64
computer he designed and built an
adapter card that plugged into the
memory expansion port of the Com-
modore. Program was a total suc-
cess. Hundreds of memory modules
were assembled and tested using this
interface without a single field fail-
ure. I was lucky to have had Laird as
a member of my team.
April 15, 2015, Paul managed Laird
at American Electronics Laboratory

.Since I had a 4.0, I was invited back to teach the course I had just competed.
I did this in the evening and Saturday while working at AEL in the day.
P R O F E S S O R , E E T H E O R Y N D M A T H , 2
Y E A R E V E N I N G D I V I S I O N A T R E T S
C O L L E G E

My internal die probe station I defined and
setup. FA on OC48 and OC192 NPI die
Worlds first membrane probe card I designed with Cas-
cade Microtech for the AT&T Clock and Data Recovery
chip wafer probe.
Uses co-planar waveguide
layout to minimize phase
dispersion.
Perfect OC48 clock and data eye diagram at wafer probe.
L A I R D R E E S E S N O W D E N : M I S C
Donald Fister
Program Manager, Program Director
| Open to new opportunities
This is a very strong recommenda-
tion for Laird. It has been my pleas-
ure to work with Laird for a number
of years in a company strategic busi-
ness unit. He provided critical solu-
tions to test set development that
supported leading edge high reliabil-
ity products. During that time he
successfully pioneered the inven-
tion / development of advanced state
of the art development and manufac-
turing test. He demonstrated keen
attention to detail and a strong com-
mitment balancing cost and quality.
Any company would be fortunate to
acquire is services.
Dr.Yi Cai
Test Engineering Director at Avago
Technologies
I worked with Laird in the first few
years of my career starting at Lucent
Technologies Bell Labs. As a newly
grad with a Ph.D., I took on a job to
define the upcoming CMOS GHz
SerDes testing in 2000. Laird's prac-
tical experience in the 2.5G/10G
SONET test gave me a healthy dose
of reality in GHz production test
challenges. I learnt a lot of the GHz
Signal Integrity concepts in PCB
design and connector launch tech-
nique from Laird. Later on, we
worked together in selecting an ATE
platform to construct a hybrid ATE
test solutions with add-on instru-
ment. That is for multi-GHz SerDes
embedded in larger ICs, when the
technology moved from GaAs to
CMOS. I have been impressed by
Laird's attention to details and prac-
tical knowledge to foresee SI issues
in a production environment.
May 20, 2015, Yi worked with Laird
at Bell Labs AT&T/Lucent Tech-
nologies

Exemplar analog chip block by block experience embedded test
in larger integration projects
Reference and Bias: I developed tests to trim and set and verify the Bandgap voltage and current divider ratios
settings in NVM (OTP)
PLL,: I tested Xtal drive circuits for FUNDAMENTAL and THIRD OVERTONE external xtals, set and verify OTP drive levels and pro-
grammed Ct.
General Purpose ADC: Verified performance in test, set and calibrate conversion.
LDO: test and verify, stress test.
I2C, one pin and SPI die protocols, I wrote my own test and measurement macro’s to generate hundred thousand
lines of commented mixed signal test and measurement vectors from opcode/operand lists in Excel !
OTP: write OTP programming sequence, verify, auto adapt to partially programmed parts, verification of programmed parts in retest,
power up sequence testing and debug, device configuration bits, as well as device/design centering bits, partial register programming and
mutli register programming: ,set, read pass fail test and measure SRAM (microcode in test pattern, then set OTP). Verify OTP pre and
post sequence.
WATCHDOG: Verify internal monitor alarms function such as OTP failure, thermal trip, integrity BIST check.
GPIO: test and set output levels for all variants of output drivers, design multifunctional load board for all device terminations such as
LVDS, LVPECL, CML CMOS, HCSL etc
SMPS: Set output levels, load test outputs, noise etc.
Please ctrl+click for Device programming, test and set Test Exceutive, an ex-
ample

TEST PLATEFORMS
Silabs:
Teradyne J750, I extended RF and analog performance on J750, such as RF peak detector, Duty Cycle
balance as needed to meet cost bulletins for low cost, high performance multi site testing
Wrote drivers and added E5052 waveform analyzer to J750
Program J750, highly advanced mixed signal test
Teradyne J750, reduced HRAM acquisition time by orders of magentude by finding broken hardware in
the tester and creating a work around to put the hardware back into use, extended HRAM mamory depth
from 256 to 3000 *11/12 bytes.
Catalyst.
Wrote drivers and added E5052 to RF Catalyst
Program Cat in C
Lab Setups
AT&T Bell Labs
LTX Fusion HF (RF Mixed Signal test)
Rack and Stack automation and lab setup, HP93000.
Work with test vendors to evaluate their test platforms
Vector Network analyzer TDR S parameters with (de embed fixtures).
Smith Chart RnS Probe, BERT RnS Probe
AEL Automate Rack and Stack test instruments:
Tracking Spectrum Analyzer (programmed as M by N spurious detector, tracker)
Frequency Synth
Vector Network Analyzer
Tracking YIG filter
Scalar Netwiork Analyzer
GPIB: Quad Power supplies, DMM
Switching Scanner
RF SWITCHING NETWORKS, bias Tee’s, Couplers, circulators, bridges etc
Noise figure
Smith Chart VNA measurements

ANALOG CIRCUITS
SILABS ANALOG
analog power circuits are block whithin ASIC CHIPS: Si500 crystal less anyrate clock chip,
Si5300 any rate clock chip, Si5364, Si5320: jitter attenuators, communication oscillatorstest
plan for framing communication chip (L1 and L2 protocols)
AT&T analog devices:
CDR (Clock Data Recovery chip) (OC48), 2.488 Gb/s
Limiting Amp OC192, OC48
Transimpedance Amp
Laser Driver: for OC48 and OC192 phy layer.
VIDEO REAL TIME SWITCH MATRIX.
Probe development to 80 GHz wafer probe (for wave guide distributed amplifier), coplanar
waveguide, microstrip test interface etc.
AEL:
Dual RF converter (band selectable RF filters, Ceramic filter design, RF Amplifiers, RF to IF
converters, ~DC to millimeter band,
Log Video amplifier
Earth/SAT display driver,
SUBACS memory module.
RF Detectors
Anchoic chamber testing
Transmission Gates, Drivers, HIgh Band oscillator tune and test, indium tuning, dieletric tun-
ing and dual wirebond transistor gate impedance coupling tuning for High Band oscillator, ra-
dar detector.
In addition i have designed test circuits with Op Amps, Analog devices such as 555, discrete
transistors, crowbar circuits., power supply test circuits to protect burn in boards, current fold
back, now these are circuits i have designed and simulated (simulate for thermal run away
while operating in burn in ovens, check crow bar and limiting regulation) and built for testing
primary ASIC devices.

Pure DIGITAL EXPERIENCE:
Real Time Video Switch matrix.
Configurable high speed buffer
Memory mapped IO tester design and construction and programming, (assembly and basic)
CPU burn in event monitor
RF Experience:
Defense Electronics
High band oscillator tuning (adjust parallel wire bond spacing (mutual inductance) .
DC to millimeter RF converter module, test, FA, Ceramic filter design.
Design and built spurious M by N identifier test set, chech spur ID and levels for pass fail, used
YIG
preselector .
Amplifier modules.
Heads up phased array avionics approach warning.

MIXED SIGNAL EXPEREINCE:
Create TEST FLOWS and software for ASIC devices with NVM, OTP memory to set and cen-
ter device performance to data sheet specs, compensate for process variation, set device
characteristics (as an example, output buffer type), program such things as bandgap voltage
reference etc , frequency for clocks etc., write macro to autogenerate test vectors with analog
microcode and pass fail , read write capability for any typoe of device communication protocol,
thus creating a huge reduction in test development time and reducing pattern errors to zero
Develop test for Si5300 Any Rate clock:
Fractional divide by M DLL
Built in jitter test
Phase correction
Multiple output buffer formats
Measure and correct process variations such as
Bandgap voltage
IRint
Xtal driver
Buffer levels
Etc
SI500 any rate, more complex
Digital and analog measurement block built into die to minimize line settling time
Program blocks, , correct metrology on each device, before using blocks
Correct more functions including all out buffer specs.
Multiple output buffers
Device is fully thermally profiled I wrote a new profile to reduce profile time from 1.2 seconds to
300 milliseconds !,
Verify polynomial correction factors.
Reduce test flow to single room insertion flow, by removing cold and hot fails at room.
(calculated corner material, lot sample quantities to guarantee reliability with flow removal
Develop inline second temp sampling without requiring a second pass of sample lots.
Add low jitter (sub picoseconds test)
Add thermal die detection.
Add RF peak detector
RF Buffer
Write programs as above
Verify die temp during socket test

PROCESS EXPERIENCE:
CMOS FA in conjunction with new device bring up in new (smaller geometry) process
SiGi: FA for New product introduction
BiCMOS FA for New product introduction
GaAs SARGIC: FAB BRINGUP
GaAS: CVD Yield improvement
GaAs ERGIC: Yield improvement.
FUNCTION EXPERIENCE
New Product bring up and debug
New product deployment to full high volume production
Quality Verification and Testing
Burn in board design with overvoltage crowbar protection also MCU monitoring option
LAB verification, failure eanalysis IV curves TEM photonic emission, microscope
Thermal analysis die
Customer returns
DFT
Test set design and conbtruction
Production release
Production failure risk mitigation
IDDQ, Vbump (must by pass regulator)
New Process debug
New Test platform bring up
Yield optimization
Data analysis, reports
Executive summaries
Engineering documents
ISO 9000

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