Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

1. Conditional-Boosting Flip-Flop for Near-Threshold Voltage
Application
ABSTRACT:
A conditional-boosting flip-flop is proposed for ultra-low voltage application
where the supply voltage is scaled down to the near-threshold region. The
proposed flip-flop adopts voltage boosting to provide low latency with reduced
performance variability in the near threshold voltage region. It also adopts
conditional capture to minimize the switching power consumption by eliminating
redundant boosting operations. Experimental results in a 65-nm CMOS process
indicated that the proposed flip-flop provided up to 72% lower latency with 75%
less performance variability due to process variation, and up to 67% improved
energy-delay product at 25% switching activity compared with conventional pre
charged differential flip-flops. The proposed architecture of this paper is analysis
the logic size, area and power consumption using tanner tool.
SOFTWARE IMPLEMENTATION:
 Tanner EDA