Lec9 Intro to Computer Engineering by Hsien-Hsin Sean Lee Georgia Tech -- Combinational Logic
1. ECE2030
Introduction to Computer Engineering
Lecture 9: Combinational Logic, Mixed Logic
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech
2. Logic Design
• Logic circuits
– Combinational
– Sequential
Combinational
circuits
N
inputs
M
outputs
Combinational
circuits
inputs outputs
Storage
Element
delaydelay
3. Combinational Logic
• Outputs, “at any time”, are determined by the input
combination
• When input changed, output changed immediately
– Note that real circuits are imperfect and have “propagation delay”
• A combinational circuit
– Performs logic operations that can be specified by a set of Boolean
expressions
– Can be built hierarchically
Combinational
circuits
N
inputs
M
outputs
8. Mixed Logic
• Enable component reuse
• Allow a digital logic circuit designer to
implement a combinational logic with
– Only NAND gates
– Only NOR gates
– Only NAND and NOR gates
14. Mixed Logic (3)
• Convert each gate to the desired gate
– If only NAND gate is available, insert a bubble in
front of the AND gate
– If only OR gate is available, insert a bubble in
front of the OR gate
• Using DeMorgan’s Law in the process
– OR ⇒ NAND: by adding 2 bubbles on the inputs
side of OR
– AND ⇒ NOR: by adding 2 bubbles on the inputs
side of the AND
15. Example: Mixed Logic (3)
DABCD)C,B,F(A, +=
B
C
D
A
Assume this design usesAssume this design uses NANDNAND gatesgates onlyonly
==
16. Mixed Logic (4)
• Balance the bubbles on each wire, i.e. even
out the number of bubbles on every wire
• If there is odd number of bubbles on a wire,
add an inverter (i.e. a bubble)
• And remove those “vertical bars with
bubbles” which are used to help only, not in
the circuits
17. Example: Mixed Logic (4)
DABCD)C,B,F(A, +=
B
C
D
A
Assume this design usesAssume this design uses NANDNAND gatesgates onlyonly
18. How about Inverters?
• Inverters can be implemented by either a NAND or a
NOR gate
– Wiring the inputs together
≡≡
≡≡
19. Example: Mixed Logic (Final)
DABCD)C,B,F(A, +=
B
C
D
A
Assume this design usesAssume this design uses NANDNAND gatesgates onlyonly
20. Example: Mixed Logic (Final)
DABCD)C,B,F(A, +=
B
C
D
A
Assume this design usesAssume this design uses NANDNAND gatesgates onlyonly
6 NAND gates are used6 NAND gates are used
21. Mixed Logic
• How about build the prior circuits with only
NOR gates?
23. Example: Mixed Logic (2)
DABCD)C,B,F(A, +=
B
C
D
A
Add vertical bar forAdd vertical bar for
each inversioneach inversion
24. Example: Mixed Logic (3)
DABCD)C,B,F(A, +=
B
C
D
A
Assume this design usesAssume this design uses NOR gatesNOR gates onlyonly
==
Convert each gateConvert each gate
to a NORto a NOR
25. Example: Mixed Logic (4)
DABCD)C,B,F(A, +=
B
C
D
A
Assume this design usesAssume this design uses NOR gatesNOR gates onlyonly
Balance number ofBalance number of
Bubbles on each wireBubbles on each wire
26. Example: Mixed Logic (4)
DABCD)C,B,F(A, +=
Assume this design usesAssume this design uses NOR gatesNOR gates onlyonly
Balance number ofBalance number of
bubbles on each wirebubbles on each wire
and substitute all gatesand substitute all gates
to NORto NOR
B
C
D
A
27. Example: Mixed Logic (Final)
DABCD)C,B,F(A, +=
Assume this design usesAssume this design uses NOR gatesNOR gates onlyonly
B
C
D
A
7 NOR gates are used7 NOR gates are used
28. Mixed Logic Example II (1)
))DC(BACBAF ⋅++++=
C
D
A
B
Implement the logic circuits by ignoring all inversionsImplement the logic circuits by ignoring all inversions
29. Mixed Logic Example II (2)
))DC(BACBAF ⋅++++=
C
D
A
B
Add vertical bar/bubble for each inversionAdd vertical bar/bubble for each inversion
30. Mixed Logic Example II (3)
))DC(BACBAF ⋅++++=
C
D
A
B
Assume this design usesAssume this design uses NANDNAND gatesgates onlyonly
31. Mixed Logic Example II (4)
))DC(BACBAF ⋅++++=
C
D
A
B
Balance the bubbles for each wire w/ invertersBalance the bubbles for each wire w/ inverters
32. Mixed Logic Example II (5)
))DC(BACBAF ⋅++++=
C
D
A
B
Remove the vertical bars/bubblesRemove the vertical bars/bubbles
33. Mixed Logic Example II (6)
))DC(BACBAF ⋅++++=
C
D
A
B
Replace all the gates toReplace all the gates to NAND gatesNAND gates
34. Mixed Logic Example II (7)
))DC(BACBAF ⋅++++=
C
D
A
B
Final mixed logic uses 11 NAND gatesFinal mixed logic uses 11 NAND gates
(one of them is a triple-input NAND gate)(one of them is a triple-input NAND gate)
35. Mixed Logic Example III (1)
DBACAF =
B
D
A
C
Implement the logic circuits by ignoring all inversionsImplement the logic circuits by ignoring all inversions
36. Mixed Logic Example III (2)
DBACAF =
B
D
A
C
Add vertical bar/bubble for each inversionAdd vertical bar/bubble for each inversion
37. Mixed Logic Example III (3)
DBACAF =
B
D
A
C
Assume this design usesAssume this design uses NOR gatesNOR gates onlyonly
38. Mixed Logic Example III (4)
DBACAF =
B
D
A
C
Balance the bubbles for each wire w/ invertersBalance the bubbles for each wire w/ inverters
39. Mixed Logic Example III (5)
DBACAF =
B
D
A
C
Remove the vertical bars/bubblesRemove the vertical bars/bubbles
40. Mixed Logic Example III (6)
DBACAF =
B
D
A
C
Replace all the gates toReplace all the gates to NOR gatesNOR gates
41. Mixed Logic Example III (7)
DBACAF =
B
D
A
C
Final mixed logic uses 9 NOR gatesFinal mixed logic uses 9 NOR gates