Analysis about combination circuit

1. Combinational Logic
Chapter 5

2. Digital Circuits 2
4.1 Introduction
 Logic circuits for digital systems may be
combinational or sequential.
 A combinational circuit consists of logic gates
whose outputs at any time are determined
from only the present combination of inputs.

3. Digital Circuits 3
4.2 Combinational Circuits
 Logic circuits for digital system
 Sequential circuits
 contain memory elements
 the outputs are a function of the current inputs and the
state of the memory elements
 the outputs also depend on past inputs

4. Digital Circuits 4
 A combinational circuits
 2
n
possible combinations of input values
 Specific functions
 Adders, subtractors, comparators, decoders, encoders,
and multiplexers
 MSI circuits or standard cells
Combinational
Logic Circuit
n input
variables
m output
variables

5. Digital Circuits 5
4-3 Analysis Procedure
 A combinational circuit
 make sure that it is combinational not sequential
 No feedback path
 derive its Boolean functions (truth table)
 design verification
 a verbal explanation of its function

6. Digital Circuits 6
 A straight-forward procedure
F2 = AB+AC+BC
T1 = A+B+C
T2 = ABC
T3 = F2'T1
F1 = T3+T2

7. Digital Circuits 7
 F1 = T3+T2 = F2'T1+ABC
= (AB+AC+BC)'(A+B+C)+ABC
= (A'+B')(A'+C')(B'+C')(A+B+C)+ABC
= (A'+B'C')(AB'+AC'+BC'+B'C)+ABC
= A'BC'+A'B'C+AB'C'+ABC
 A full-adder
 F1: the sum
 F2: the carry

8. Digital Circuits 8
 The truth table

9. Digital Circuits 9
4-4 Design Procedure
 The design procedure of combinational circuits
 State the problem (system spec.)
 determine the inputs and outputs
 the input and output variables are assigned symbols
 derive the truth table
 derive the simplified Boolean functions
 draw the logic diagram and verify the correctness

10. Digital Circuits 10
 Functional description
 Boolean function
 Logic minimization
 number of gates
 number of inputs to a gate
 propagation delay
 number of interconnection
 limitations of the driving capabilities

11. Digital Circuits 11
4-5 Binary Adder-Subtractor
 Half adder
 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10
 two input variables: x, y
 two output variables: C (carry), S (sum)
 truth table

12. Digital Circuits 12
 S = x'y+xy'
C = xy
 the flexibility for implementation
 S=xy
 S = (x+y)(x'+y')
 S' = xy+x'y'
S = (C+x'y')'
 C = xy = (x'+y')'

13. Digital Circuits 13

14. Digital Circuits
Half Adder using NAND
14

15. Digital Circuits
Half Adder using NOR
15

16. Digital Circuits 16
 Full-Adder
 The arithmetic sum of three input bits
 three input bits
 x, y: two significant bits
 z: the carry bit from the previous lower significant bit
 Two output bits: C, S

17. Digital Circuits

18. Digital Circuits
Implementation of Full Adder in Sum of
Product
18

19. Digital Circuits
Implementation of Full Adder with 2 Half
Adder & an OR Gate

20. Digital Circuits
Full Adder using NAND
20

21. Digital Circuits
Full Adder using NOR
21

22. Digital Circuits 22
 Binary adder with Ripple Carry Propagation

23. Digital Circuits 23
 Look Ahead Carry propagation
 when the correct outputs are available
 the critical path counts (the worst case)
 (A1,B1,C1) > C2 > C3 > C4 > (C5,S4)
 > 8 gate levels

24. Digital Circuits 24
Look Ahead Carry propagation
 Reduce the carry propagation delay
 employ faster gates
 look-ahead carry (more complex mechanism, yet
faster)
 carry propagate: Pi = AiBi
 carry generate: Gi = AiBi
 sum: Si = PiCi
 carry: Ci+1 = Gi+PiCi
 C1 = G0+P0C0
 C2 = G1+P1C1 = G1+P1(G0+P0C0)
= G1+P1G0+P1P0C0
 C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

25. Digital Circuits 25
 Logic diagram

26. Digital Circuits 26
 4-bit carry-look ahead adder
 propagation delay

27. Digital Circuits 27
Binary subtractor Or Adder
 A-B = A+(2’s complement of B)
 4-bit Adder-subtractor
 M=0, A+B; M=1, A+B’+1

28. Digital Circuits 28
 Overflow
 The storage is limited
 Add two positive numbers and obtain a negative
number
 Add two negative numbers and obtain a positive
number
 V = 0, no overflow; V = 1, overflow
Example:

29. Digital Circuits
Serial Addition (D Flip-Flop)
 Slower than
parallel
 Low cost
 Share fast
hardware
on
slow data
 Good for
multiplexed
data

30. Digital Circuits
Serial Addition (D Flip-Flop)
 Only one full
adder
 Reused for each
bit
 Start with low-
order bit addition
 Note that carry
(Q) is saved
 Add multiple
values.
 New values
placed in shift
register B

31. Digital Circuits
Serial Addition (D Flip-Flop)
 Shift control
used to stop
addition
 Generally not a
good idea to
gate the clock
 Shift register
can be arbitrary
length
 FA can be built
from combin.
logic

32. Digital Circuits 32
4-6 Decimal Adder
 Add two BCD's
 9 inputs: two BCD's and one carry-in
 5 outputs: one BCD and one carry-out
 Design approaches
 A truth table with 2^9 entries
 use binary full Adders
 the sum <= 9 + 9 + 1 = 19
 binary to BCD

33. Digital Circuits 33
 BCD Adder: The truth table

34. Digital Circuits 34
 Modifications are needed if the sum > 9
 C = 1
 K = 1
 Z8Z4 = 1
 Z8Z2 = 1
 modification: (10)d or +6
C = K +Z8Z4 + Z8Z2

35. Digital Circuits 35
 Block diagram

36. Digital Circuits 36
Excess-3 Adder
 Excess-3 code = BCD + (3)10
 If carry = 0, we add to excess-3 digit then we have to
subtract (3)10 = (0011)2 from the sum for once.
Because, each of the two digit had excess of 3
values. So during addition, 3 is added twice in the
sum whereas, 3 should be added once.
 If carry =1, then we need to add (0011) with the sum
to get the correct digit

37. Digital Circuits
37
Design Exercise
2-bits x 2-bits Multiplier

38. Digital Circuits 38
Terms
2
X 3
--------------
6
Mutiplicand
Multiplier
Product

39. Digital Circuits 39
Multiplication in binary form?
1. Rewrite the multiplication in binary
form.
1. Sketch the black box view.
1. The multiplier multiplies two __?__
bits numbers.

40. Digital Circuits 40
2-bits x 2-bits Multiplier Design
 Two techniques:
 Using the standard K-Map
 Using Arrays (cascaded
approach)

41. Digital Circuits 41
Method A:
Using the K-Map Technique
 Sketch the bLack box.
 Sketch the Truth Table for a 2-bit “multiplier” and 2-
bit “multiplicand”.
 Input (Multiplier) = A1 and A0
 Input (Multiplicand) = B1 and B0
 Output (4-bits) = S3, S2, S1 and S0 or S[3..0]
 Using K-Maps, obtain the boolean expression for
each output.
 Sketch the schematic diagram.

42. Digital Circuits 42
Method B:
Using the Array (Cascaded) Technique
 Create the 2x2 multiplier using Full ADDERS.
Design “Smart”

43. Digital Circuits 43
… tHE cONcEpt
A1 A0
B1 B0
x
A1B0 A0B0
A1B1 A0B1
+
S0
S1
S2
S3
C
C

44. Digital Circuits 44
A 2-Bit by 2-Bit Binary Multiplier

45. Digital Circuits 45
AND
comput
es A0
B0
Half adder
computes
sum. Will
need FA
for larger
multiplier.

46. Digital Circuits 46
 4-bit by 3-bit binary multiplier
Fig. 4.16
Four-bit by three-bit binary
multiplier.

47. Digital Circuits
47
The 4-bits x 4-bits
Multiplier
Using Array 2x2

48. Digital Circuits 48
Multiplier Product
 The product of m-bit x n-bit numbers
is an (m+n)-bit number.
=> The product of two 4-bit numbers
is an 8-bit number.

49. Digital Circuits 49
How about this one?
13
X 11
--------------
143
Mutiplicand
Multiplier
Product

50. Digital Circuits 50
1
1
1
1
(143) Product
1
1
1
0
0
0
1
1
0
1
1
0
0
0
0
1
0
1
1
0
1
1
(11) multiplier
1
0
1
X
(13) multiplicand
0
1
1
Partial products

51. Digital Circuits 51
S0
S1
S2
S3
S4
S5
S6
S7
A0B3
A1B3
A2B3
A3B3
A0B2
A1B2
A2B2
A3B2
A0B1
A1B1
A2B1
A3B1
A0B0
A1B0
A2B0
A3B0
B0
B1
B2
B3
A0
A1
A2
A3

52. Digital Circuits 52
 Design a 4-bits x 4-bits multiplier using the Array
(cascaded) technique, by utilizing:
 The 2-bits x 2-bits Multiplier and full adder
designed earlier.
 Hints : Look back at the concept of 2x2 multiplier.
Take the same step.

53. Digital Circuits
Ripple-Carry Array Multiplier
FA
A2B
1
A0B
0
FA
A3B
1
FA
A1B
2
C
C
S
A2B
1
HA
S
FA
A3B
2
FA
A2B
1
C
C
S
A0B
3
FA
A3B
3
FA
A2B
3
C
C
S
C
HA
A1B
3
C
S
HA
FA
C C
HA
A0B
2
C
S
A2B
1
A2B
1
A2B
1
A2B
1
C
S S S
S
S
S
P0
P7 P6 P5 P4 P3 P2 P1

54. Digital Circuits 54
Calculation of Multiplication Time
