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# Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

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### Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

1. 1. Minimum Cost Fault TolerantAdder Circuits in Reversible Logic Synthesis Sajib Kumar Mitra* Department of Computer Science and Engineering Faculty of Engineering and Technology University of Dhaka, Dhaka-1000, Bangladesh E-mails: sajibmitra.csedu@yahoo.com, farhan717@cse.univdhaka.edu * Corresponding Author and Presenter
2. 2. Purposes• Minimization of Quantum Cost• Fault Tolerant Circuit• Reduction of Critical Path Delay• Reduction of Number of Gates• Garbage Outputs Optimization
3. 3. Overview• Reversible and Quantum Computing• Quantum Realization of Reversible Circuits• Fault Tolerant Mechanism• Proposed Designs of Adder Circuits• Performance Analysis• Conclusion
4. 4. Reversible and Quantum Computing
5. 5. Reversible Computing • Equal number of input states and output states • Preserves an unique mapping between input and output vectors for any Reversible circuit • One or more operations can be united called Reversible Gate • (N x N) Reversible Gate has N number of inputs and N number of outputs where N= {1, 2, 3, …}[1] A. K. Biswas, M. M. Hasan, A. R. Chowdhury, and H. M. H. Babu, “Efficient approachesfor designing reversible binary coded decimalimplement in a single adders,”Microelectronics Jounrnal, vol. 39, no. 12, pp. 1693–1703, December 2008.
6. 6. Reversible Computing…Fig. 1: Basic difference between Irreversible and Reversible Circuits• Limitation • Feedback is strictly restricted • Fan-out must be one always
7. 7. Reversible Computing…Fig. 2: Popular Reversible gates
8. 8. Quantum ComputingIn Quantum Computing, encode information as a series ofquantum-mechanical states such as spin directions ofelectrons or polarization orientations of a photon thatmight represent as or might represent a superposition ofthe two values.Encoded data is represented by qubits rather than bitswhich can perform certain calculations exponentiallyfaster than conventional computing. q =α 0 + β 1[2]W. N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, “Quantum logic synthesis bysymbolic reachability analysis,” in 41st Conference on (DAC’04), Design AutomationConference, May 2004, pp. 838–841.
9. 9. Quantum Computing…Quantum Computation uses matrix multiplication ratherthan conventional Boolean operations and the informationmeasurement is realized by calculation the state of qubits .The matrix operations over qubits are simply specifies byusing quantum primitives. For example, Fig. 3: Reversible behavior of Quantum matrix operation
10. 10. Quantum Computing… Input Output A B P Q 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0 Input/output Symbol Pattern 00 a 01 b 10 c 11 dFig. 4: Working Principle of Unitary Controlled NOT (UCN)
11. 11. Quantum Realization of Reversible Circuits
12. 12. Quantum Cost• Quantum Cost (QC): Total number of 2x2 quantum primitives (4x4 unitary matrices) which are used to form equivalent quantum circuit of any Reversible Circuit. Fig. 5: Several Quantum Primitives[3] M. Perkowski and et al, “A hierarchical approach to computer-aided design of quantumcircuits,” in 6th International Symposium on Rep-resentations and Methodology of FutureComputing Technology, 2003, pp. 201–209.
13. 13. Orientation of Quantum Gates The attachment of SRN (Hermitian Matrix of SRN) and EX-OR gate on the same line generates symmetric gate pattern has a cost of 1. Here T= V or V+Fig. 6: Difference interactions between Quantum Primitives
14. 14. Quantum Cost of Reversible gatesFig. 7: Equivalent Quantum Circuits of Reversible Gates
15. 15. Working Principle of Quantum Circuit How does Quantum circuit work? Fig. 8: Toffoli Gate and corresponding Quantum Circuit
16. 16. Working Principle of Quantum Circuit… INPUT OUTPUT A B R 0 0 C 0 1 C 1 0 C 1 1 C’ Fig. 9: Working Principle of Quantum Equivalent of TG
17. 17. Working Principle of Quantum Circuit… INPUT OUTPUT A B R 0 0 C 0 1 C 1 0 C 1 1 C’ Quantum Cost of Toffoli Gate is 5
18. 18. Working Principle of Quantum Circuit…Alternate representation of Quantum circuit of TG…
19. 19. Proposed Quantum Circuit of NFTFig. 9: Quantum Realization of NFT Gate (QC= 5)
20. 20. Proposed Quantum Circuit of NFT…
21. 21. Proposed Quantum Circuit of NFT…
22. 22. Proposed Quantum Circuit of NFT…
23. 23. Proposed Quantum Circuit of NFT…
24. 24. Proposed Quantum Circuit of NFT…
25. 25. Proposed Quantum Circuit of NFT…
26. 26. Proposed Quantum Circuit of NFT…
27. 27. Proposed Quantum Circuit of NFTFig. 9: Quantum Realization of NFT Gate (QC= 5)
28. 28. Fault Tolerant Mechanism
29. 29. Fault Tolerant MechanismPreserves same parity between Input and Output vectors over one to one mapping of Reversible circuit. Fig. 10: Fault Tolerant circuit preserves same parity between input and output vectors[4] B. Parhami, “Fault tolerant reversible circuits,” in In Proc. of 40 th Asimolar ConferenceSignals, Systems and Computers. Pacific Grove, CA, 2006, pp. 1726–1729.
30. 30. Fault Tolerant Mechanism...Let, Iv and Ov are input and output vectors of a reversible circuit, so the relation is Iv↔Ov.But to be a Reversible Fault Tolerant circuit, itself must preserve following equation: I1 ⊕ I 2 ⊕ ⊕ I n = O1 ⊕ O2 ⊕ ⊕ Onwhere Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On} Input Parity = Output Parity
31. 31. Fault Tolerant Mechanism…Fig. 11: Most Popular Fault Tolerant Gates
32. 32. Fault Tolerant Mechanism… INPUT OUTPUT A B C P Q R 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0A ⊕ B ⊕C = P ⊕Q ⊕ R 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1
33. 33. Fault Tolerant Mechanism…Verification of the following equation: A ⊕ B ⊕C = P ⊕Q ⊕ R Circuit without Fault Circuit with Faulty Output Fault detection of FRG gate
34. 34. Fault Tolerant Mechanism… QC= 2 QC=5 QC= 5 QC= 7
35. 35. Proposed Design of Adder Circuits
36. 36. Proposed Design of Full AdderReversible Fault Tolerant Full Adder 2 2 2 5 2 2 5 2Fig. 12: Proposed Design of Fault Tolerant Adder Circuit
37. 37. Comparison with Existing Design Comparison with Existing [5] Fault Tolerant Design 7 7 Single NFT Full Adder 2 SNFA 2 5 2[5] M. S. Islam, M. M. Rahman, Z. begum, and M. Z. Hafiz, “Efficient approaches for designingfault tolerant reversible carry look-ahead and carry-skip adders,” MASAUM Journal of Basic andApplied Sciences, vol. 1, no. 3, 2009.
38. 38. Proposed Design of Carry Skip AdderReversible Fault Tolerant Carry Skip Adder (RFT-CSA) Fig. 13: Proposed Design of Fault Tolerant Carry Skip Adder
39. 39. Delay Calculation of RFT-CSADelay Optimization of Fault Tolerant Carry Skip Adder 4 5 9 8 7 6 Fig. 14: Delay Calculation of RFT-CSA
40. 40. Performance Analysis of RFT-CSA 140 Gates Garbage Delay Quantum Cost 120 100 80 U n s 60 ) ( t i 40 20 0 Proposed Existing [5] Exising [6] Existing [7]Fig. 15: Compare with existing designs of Carry Skip Adder[6] P. K. Lala, J. P. Parkerson, and P. Charaborty, “Adder designs using reversible logicgates,” WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, June 2010.[7] J. W. Bruce et al., “Efficient adder circuits based on a conservative re-versible logicgates,” in ISVLSI ’02: Proceedings of the IEEE Computer Society Annual Symposium on VLSI. Washington, DC, USA, 2005, pp. 83–88.