SGU - Material Science Part 5 [Special Subject_ Nano Material]

SWISS GERMAN UNIVERSITY
Hernanto Wiryomijoyo / MT / Bachelor / Material Science
Rev. 2– 01/05/07
1
MATERIAL SCIENCE
Part 5 [Special Subject: Introduction to Application
of Nano Material Composite and Technology]
Main References:
1. http://www.crnano.org
2. http://www.intel.com/research/silicon
3. http://www.platit.com

Rev. 2– 01/05/07
2
Nanotechnology is the projected ability to make things from the bottom up, using techniques and
tools that are being developed today to place every atom and molecule in a desired place. If this form
of molecular engineering is achieved, which seems probable, it will result in a
manufacturing revolution. It also has serious economic, social, environmental, and military
implications.
The principles of physics, as far as I can see, do not speak against the possibility of
manuvering things atom by atom. It is not an attempt to violate any laws; it is something, in
principle, that can be done; but in practice, it has not been done because we are too big. —
Richard Feynman, Nobel Prize winner in physics
When Eric Drexler (right) popularized the word 'nanotechnology' in the 1980's, he was talking about
building machines on the scale of molecules, a few nanometers wide—motors, robot arms, and even
whole computers, far smaller than a cell. Drexler spent the next ten years describing and analyzing
these incredible devices, and responding to accusations of science fiction
What is nanotechnology?
Meanwhile, mundane technology was developing the ability to build simple structures on a molecular scale. As nanotechnology
became an accepted concept, the meaning of the word shifted to encompass the simpler kinds of nanometer-scale technology. The
U.S. National Nanotechnology Initiative was created to fund this kind of nanotech: their definition includes anything smaller than
100 nanometers with novel properties.
Nanotechnology is often referred to as a general-purpose technology. That’s because in its mature form it will have significant
impact on almost all industries and all areas of society. It offers better built, longer lasting, cleaner, safer, and smarter products for
the home, for communications, for medicine, for transportation, for agriculture, and for industry in general.

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(A) shows a hand holding a computer chip. This is
shown magnified 100 times in
(B) Another factor of 100 magnification
(C) shows a living cell placed on the chip to show
scale. Yet another factor of 100 magnification
(D) shows two nanocomputers beside the cell. The
smaller (shown as block) has roughly the same
power as the chip seen in the first view; the larger
(with only the corner visible) is as powerful as
mid-1980s mainframe computer. Another factor
of 100 magnification
(E) shows an irregular protein from the cell on the
lower right, and a cylindrical gear made by
molecular manufacturing at top left. Taking a
smaller factor of 10 jump,
(F) shows two atoms in the protein, with electron
clouds represented by stippling. A final factor of
100 magnification
(G) reveals the nucleus of the atom as a tiny speck.
The Power of Ten

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Yield Trend for Intel®
Logic Technologies

Rev. 2– 01/05/07
5
90 Nanometer: The World's Most
Advanced Chip-Making Process from Intel®
• Intel has been driving the pace of Moore's Law by introducing a new process generation every
two years. The 90 nanometer (nm) process is the next generation after the 0.13-micron
process. 0.13-micron is the process Intel currently uses to make the bulk of its
microprocessors.
• Intel has announced the integration of strained silicon to improve the performance of
transistors on the 90-nm process technology, the most advanced semiconductor
manufacturing process in the industry.
• Technology and Manufacturing Group, and director of process architecture and integration
adding, "The transistors use features that other companies have yet to match, such as a 1.2-
nm gate oxide thickness, nickel silicide for low resistance, and strained silicon
technology."
• 90-nm process combines higher-performance, lower-power transistors, strained silicon, high-
speed copper interconnects and a new low-k dielectric material. This is the first time all of
these technologies will be integrated into a single manufacturing process.

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Transistor Strain Techniques
Legends:
S: Source; D: Drain; G: Gate

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Intel's Strained Silicon Transistors
• A unique selectively deposited SiGe Source-Drain structure induces
channel strain in PMOS devices, improving drive current by 25%
relative to non-strained devices.
• A high stress Si3N4 cap layer induces channel strain in NMOS
devices, improving drive current by 10% relative to non-strained
devices.
• NMOS and PMOS transistors are optimized separately for high
performance using this approach to strain engineering and the added
process cost is only ~2%.
• This approach to transistor strain engineering is scalable to future
generations.

Rev. 2– 01/05/07
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90 nm Generation Transistors

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9
90 nm Generation Interconnects

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90 nm Generation Transistors
 consider the behaviour of silicon atoms-they form
an orderly grid-like pattern or lattice structure. Intel
engineers strain or stretch this lattice, allowing
electrons to flow faster with less resistance.
 In NMOS devices (N for negative) the signal
carriers, or electrons, have a negative charge.
Current is on when a NMOS transistor gate is at
high voltage, and off when its gate is at low voltage.
 In PMOS (P for positive) devices, the signal carriers
are "holes," or an absence of electrons. The current
in a PMOS transistor flows opposite to that of an
NMOS transistor. It is off when its gate voltage is
high and on when its gate voltage is low.
 The Intel process stresses the crystal lattice
differently for NMOS and PMOS devices. This
results in drive current improvements of about 10
percent for NMOS and 25 percent for PMOS in
silicon manufactured with Intel's 90nm process
while increasing manufacturing costs by only two
percent.

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90 nm Integrating Strained Silicon
CMOS (complementary metal oxide
semiconductor) is Intel's process technology
for making all logic chips, such as
microprocessors and chipsets. CMOS
consists of two types of transistors, N and P.
These transistor types operate differently.
Strained silicon is a process to raise drive
current in both types of CMOS transistors.
Using a very thin layer of single-crystal silicon
with built in stress, or strain, improves drive
current, making the devices run faster. At the
molecular level, this silicon resembles a
lattice.
125-million transistor desktop processor,
code-named Prescott, and a 144-million
transistor mobile processor, code-named
Dothan.
Code Name: Prescott; Clock Speed: 2.80 – 3.40 GHz; Die Size: 112 mm2
;
L1 Cache: 16 KB; L2 Cache: 1 MB; Total Instruction: 157; Total Pipeline: 31

Rev. 2– 01/05/07
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The keyboard on any flat surfaces from where you
can carry out functions you would normally do on
your desktop computer…
And also….

Rev. 2– 01/05/07
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In the revolution of miniature computers, scientists have made great developments with
bluetooth technology... So Goodbye Laptop

Rev. 2– 01/05/07
14
Knowledge Based Small-Medium Enterprises (KB-SME)

Rev. 2– 01/05/07
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Nano-structured Coatings
The three most important structures are deposited as
 nanogradients (with continuous changing of the composition from the substrate to the top),
 nanolayers (with typical sublayer’s thicknesses of 3 – 10 nm),
 nanocomposites (nanocrystalline grains are embedded into an amorphous matrix).

Rev. 2– 01/05/07
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Nano Structured Coatings

Rev. 2– 01/05/07
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PVD-Coating of Nano-composites with Dynamic Rotating
ARC-Cathodes – [LARC®
: LAteral Rotating ARC-Cathodes]
To deposit nano-composites based on nano-layers on an industrial and economic scale, the coating
equipment have to fulfil the following basic requirements:
• The cathodes must be built in very close to each other.
• A highly ionized plasma,
• Supported by a strong magnetic field is necessary.
• This requires a very fast motion of the ARC track.

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Nano-structured Bonding Process
The magnetic field is turned by
180° and the ARC is ignited
from the back. Due to this
procedure it is possible to
clean the targets before the
coating process begins - and
to deposit the initially large
particles (droplets) against the
wall. Meanwhile the substrates
can be cleaned in intensive
plasma. The ARC will be
turned towards the tools
without being distinguished. In
effect, it is possible to shorten
the time of ion etching and to
deposit the adhesive coating
with metallic clean targets.

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Nano-structured Coating Chemical Strategy
Due to the fast ARC-spot and the use of different “pure” targets (e. g. Ti, Al or AlSi) the coating stochiometry
(composition) is freely programmable (continuously changeable = gradient) even during the processes.
• At the beginning of this LARC.-coating, the aluminium will be deposited later to the titanium, so that an
optimum adhesion coating can emerge.
• Afterwards, during the deposition, the Al-content is continuously increased, so that the hardness,
temperature stability and oxidation resistance of the coating improve.

Rev. 2– 01/05/07
20
Nano-indentation of Nano-composite (nc-Ti1-xAlxN) / (a-Si3N4)
The silicon is deposited from alloyed targets (AlSi, CrSi, TiSi etc.) After the deposition from the target,
Al and Si must be segregated. Silicon is not solved into the metallic phase, the nano-crystalline
grains (TiAlN) are embedded into an amorphous Si3N4-matrix.
For this highly ionized plasma, a
highly intensive magnetic field is
necessary. A fast ARC-spot
movement will permit a high
intensive magnetic field without
“cutting through” the targets (which
is a real danger with planar targets).
The emergence of the nano-
composite structure shows no
“space” between the nano-crystalline
grains, keeps the crystal sizes small
and the interface boundaries sharp,
therefore giving a high hardness. An
additional advantage is the stop of
crack propagation at the grain
boundaries.

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21
Hardness Increasing by Nano-composite (nc-Ti1-xAlxN) / (a-Si3N4)
• Nano-composite segregation completed
• Si is not in the metallic phase, only Si3N4
• high hardness
• high stability up to high temperatures

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Oxidation Resistance of Nano-composite Coating
Sample
No.
Konsentrasi oksigen
diukur dengan ERD
setelah deposisi
Konsentrasi oksigen diukur
dengan ERD setelah beberapa
lama
Konsentras
i oksigen
(at.%)
Umur
setelah
deposisi
(hari)
Konsentra
si oksigen
(at.%)
Umur setelah
beberapa lama
(hari)
140199 0.07 30 0.05 645
180199 0.06 26 0.05 641
260199 0.03 4 0.02 633
080499 - - 0.01 494
170599 - - 0.8 455
130999 - - 0.05 397 200 400 600 800 1000 1200
-10
0
10
20
30
40
50
60 (a) Si 3 N4= 16.18%; TiSi 2 = 9.57 %
(b) Si 3 N4= 18.01%; TiSi 2 = 14.27 %
(c) Si 3 N4=10.73%; TiSi 2 = 18.52 %
(d) Si 3 N4= 10.73%; TiSi 2 = 18.52 %
(d)
(c)
(b)
(a)
penambahanberat[mg/cm
2
]
temperatur udara kering [
o
C]

Rev. 2– 01/05/07
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Heat Resistance of Nano-composite Coating (nc-Ti1-xAlxN) / (a-Si3N4)

Rev. 2– 01/05/07
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Hardness Comparison of selected Nano-composite Material
with other strong materials.

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25
Micro Structuring of Edges of Precision Tools
after micro structuring
before micro structuring

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Application of Nano-composite Coatings
NOTE: The knowledge based small and medium size enterprises (KB-SME) are the driving forces for the development of new innovative technologies for
today’s manufacturing industry. There are a lot of innovative ideas, products and technologies, developed by KB-SME’s, they point the way ahead. This
paper shows three of them with outstanding importance:
•Integration of conventional cutting technologies and lasering into multi-functional machine centers for high performance and precision machining
•Intelligent tools measuring and reacting directly on the cutting edge
•Compact coating machines depositing nanostructured coatings directly in the manufacturing work shop
The innovative technologies of the KB-SME’s are extremely important for the manufacturing industry and for the whole society.

Rev. 2– 01/05/07
27
10-10-
50µm50µm
Fiber
10-10-
100nm100nm
WaterWater
DropletDroplet
Nano-Whiskers™ Textile

Rev. 2– 01/05/07
28
Military Industry

SGU - Material Science Part 5 [Special Subject_ Nano Material]

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