1. Miniaturisation in cMOS: Past and Future
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Miniaturisation in cMOS: Past and Future
Abstract
Computer chips can be found in almost every modern electronic device. Over the years since their
introduction they have become smaller, cheaper and more efficient, however there are limitations on
the rates of improvements that can be made to the devices. The performance of these integrated
circuits has been improving exponentially for over 40 years. In the coming years, the semi-conductor
industry must overcome several issues in order to maintain the impressive pace of improvements
made by manufacturers. The design process of CMOS devices introduces challenges in lithography,
scaling, connection, memory and circuit design, in order to maintain the pace of improvements,
solutions to such challenges must be met (Isaac, 2000).

2. Miniaturisation in cMOS: Past and Future
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Introduction
CMOS (complementary metal-oxide semiconductor) chips use complementary and symmetrical pairs
of p/n-type metal oxide semiconductor field effect transistors to perform logic functions (Sago, 2013).
The productivity of integrated circuits has improved by 25%-30% annually (Peercy, 2000), following
Moore’s Law which states that the number of transistors per square centimetre doubles every 12
months for silicon based integrated circuits. This rate of improvement discussed by Peercy is
impressive, such rates of technological advancement can’t be found in many other applications.
According to research from IBM by Randall Isaac, transistors in 1999 operate 20 times faster occupying
less than 1% of the area than those built in the 1980’s, as Isaac states this level of size reduction at
such a rate is unsustainable, in order to continuously maintain such a development rate companies
must invest large amounts of resources in cutting edge and innovative technology. The number of
components in a device directly effects the device performance, as the number of components
increases the processing power of the device increases. The increase in components per device is
largely due to the improvements in the lithographic process as well as more innovative techniques for
component formation on a device. Moore pointed out that as a result of increasing the number of
components per chip, the cost per component decreased, assuming that the increase in cost of
fabricating a chip is lower than the increase in the number of components.
The evolution of transistors used in CMOS integrated circuits was predicted with a high degree of
accuracy in 1972 at the IEEE International Electron Devices Meeting by Dennard et al. (Dennard,
Gaensslen, Kuhn, & Yu, 1972) In which they put forward a scaling theory which has driven transistor
design ever since its introduction. For any given scaling reduction factor α, Dennard et al. showed how
the voltage and levels of doping could be modified to increase the power by a factor of α, decrease
the power by a factor of α2
and keep the power density constant (Peercy, 2000). Table 1 below shows
the effect of the scaling factor α on some key device parameters, it is clear that the size of the device
has a direct effect on identifying features of the device. The lower voltage is important as it prevents
dielectric breakdown, a lower gate delay results in faster devices and a lower current means that the
device consumes less power, so it’s less likely to overheat. It is clear from the effect of the device
scaling that miniaturization in CMOS devices is something the industry aims to continue until it reaches
its limitations as it means faster, smaller and more efficient devices. This is not to say that there are
no drawbacks to using smaller and smaller devices, as CMOS devices continue to scale leakage current
becomes more and more of a major contributor to the total power consumption of the device. To
manage the increase in leakage current as devices become smaller, solutions for the leakage reduction
problem must be sought in the coming years; such solutions may well be found within in engineering
/ manufacturing techniques or at the circuit design level.
Parameter Before Scaling After Scaling
Channel Length L L / α
Channel Width W W / α
Oxide Thickness TOX Tox / α
Power Supply Vdd Vdd / α
Voltages Vto Vto / α
Current I I / α
Oxide Capacitance C C * α
Power / Unit Area P P
Gate Delay τ τ / α
Table 1 – Effects of scaling on some key device parameters (Singh & Moyal, 2014)

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Device scaling is predicted to reach approximately 10nm nodes in the years 2016-2018, the ITRS
(International Technology Roadmap for Semiconductors) is a group of semiconductor industry experts
that have suggested by 2018 the industry will be producing 8nm nodes, “heralding the era of
nanotechnology” (Michelen, 2013). The node size is the smallest feature in a transistor. Moore’s law
is predicted to come to an end soon, the semiconductor industry is reaching the limit at which the
lithographic process can be used in the standard way, as devices become smaller and smaller the
conventional processes will not hold.
Past Devices
The microprocessor was invented in 1971, in this time the clock speed has increased from
approximately 0.108MHz in 1971, to around 3.5GHz in 2013 (that’s an increase of over 32,000 times
the original speed). The clock speed is, in layman’s terms, a measure of how often we can give a
processor instructions and still have “failure free” operations (Mattson, 2014), for a 3GHz processor
allows us to give it 3 billion operations per second and will still perform as predicted.
Figure 1 shows Moore’s Law, which explores the number of transistors in Intel’s microprocessors over
the years, we can see that this development has followed Moore’s law of doubling every 2 years. The
astounding evolution of the devices are made viable by frequent downsizing of the CMOS
semiconductors, as they become smaller, they also become cheaper, use less power, and operate
faster.
The evolution of CMOS scaling has been achieved by downsizing the components of the device, in the
middle of the 1980’s 1μm was seen to be the limit due to a predicted problem in optical Lithography
amongst other predicted limitations (Iwai, 2003), over time this limit has been re-evaluated and has
been surpassed multiple times due to innovation within the industry and various technological
advancements. Table 2 shows the predicted downsizing limits over the past 45 years, as the table
suggests, each time a prediction of a limit was made it has been surpassed and appears to be
continuing to do so into nanotech devices.
Figure 1 – Moore’s Law

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Year Expected Limit Size
1971 10μm
1975 3μm
1982 1.5μm
1985 1μm
1989 800nm
1994 600nm
1995 350nm
1998 250nm
1999 180nm
2000 130nm
2002 90nm
2006 65nm
2008 45nm
2010 32nm
2011 22nm
2013 16nm
2016 11nm
Table 2 - Predicted limitations for downsizing (Siti, Binti, Habibah, Mamun, & Syedul, 2012)
One of the biggest challenges facing the industry in the past was that as the size of devices
continuously decreased, the conductors became too resistive, in order to solve this problem the
aluminium in the devices was replaced with copper, to reduce this resistivity (Michelen, 2013) at the
end of the period of what was effectively just simply scaling down devices using more advanced
lithography techniques (in around 2002).
Future Devices & Challenges
From 2002 devices began reaching beyond the 90nm mark, at this point scaling was not enough to
keep up the almost exponential development in technology, some innovation is required to keep up
the pace of development and keep the industries profits up. Some solutions explored and utilised by
the industry included computational lithography, hi-K metal gates and tri-gate transistors (Michelen,
2013). Perhaps the most important modern development in the field is the use of III-IV elements in
place of the channel, this is an important development as it allows integration of dissimilar materials
with silicon to enhance the performance of devices (Kazior, 2014). Beyond this stage (predicted to be
around 2018, as can be seen in Figure 2) the industry will have to invent new materials and
technologies, such as those seen in nano-electronics, in which carbon based materials are being
developed to design future devices.
Nano-electronics allows manipulation on dimensions of less than 100nm to create electronic
structures, the technology is emerging, innovative, and well-funded, although it is no emerging as
fast as the semi-conductor industry would like. In order for the technologies to be developed in a
time frame that the industry would like (as soon as possible realistically), they must collaborate
together. The use of graphene in devices is being widely researched, prototype structures are being
created by various industry leaders and researchers (Novoselov, et al., 2012), graphene is a gapless
semiconductor, causing problems for digital logic functions although proving useful for analogue
device applications such as low-noise amplifiers and millimetre-wave field-effect transistors (FETs)
(Banerjee, Register, Tutuc, & Basu, 2010).

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Figure 2 – Feature size over time for Semiconductors (Michelen, 2013)
Nanoscale MOSFETs aren’t without their problems, table 3 below shows several key issues and their
solutions:
Problem Solution Advantages of the solution
Poor Electrostatics Double Gate  Ability to retain gate control over
channel
 Minimize OFF-state drain-source
leakage
Poor Channel Transport High Mobility Channel  High mobility
 High drive current, low intrinsic
delay
Source / Drain parasitic
resistance
Metal Schottky source
/ drain
 Reduced extrinsic resistance
Gate leakage increased High-K dielectrics  Reduced gate leakage
Gate depletion Metal gate  High drive current
Table 3 – problems within nanotech devices and their solutions
Conclusion
The rate at which microprocessor & semiconductor technology has developed is astounding,
Moore’s law has been successful in predicting the development of devices for over 40 years
although it is now appearing to reach its limitations. Further funding for research into nano-
technology must be made available in order to develop technologies which will allow for the future
miniaturisation of devices which will still prove useful, powerful and reliable to their respective
applications. Graphene structures such as nano-tubes are providing promising research to say that it
is a recent technological development, and should provide exciting results prior to 2020, it seems
intuitive to suggest that any company which successfully develops a way to provide graphene with a
bandgap to allow for digital logic fabrication will be the industry leader for years to come.

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Bibliography
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