Encoder, Multiplexer, Exclusive-OR and Equivalence expressions

1. Combinational Logic
By
Dr. Heman Pathak
Associate Professor
Dept.of Comp. Sc.
Kanya Gurukul Dehradun

2. ENCODER
An Encoder is a combinational circuit that performs the
reverse operation of Decoder. It has maximum of 2n input
lines and „n‟ output lines. It will produce a binary code
equivalent to the input, which is active High. Therefore, the
encoder encodes 2n input lines with „n‟ bits. It is optional to
represent the enable signal in encoders.

3. 4X2 ENCODER
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and
two outputs A1 & A0. The block diagram of 4 to 2
Encoder is shown in the following figure.

4. 4X2 ENCODER
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
At any time, only one of these 4 inputs can be „1‟ in order to get
the respective binary code at the output. The Truth table of 4
to 2 encoder is shown below.

5. 4X2 ENCODER
From Truth table, we can write the Boolean
functions for each output as-
A1=Y3+Y2
A0=Y3+Y1

6. OCTAL-TO-BINARY ENCODER
Octal to binary Encoder has
eight inputs, Y7 to Y0 and
three outputs A2, A1 & A0.
Octal to binary encoder is
nothing but 8 to 3 encoder.
The block diagram of octal
to binary Encoder is shown
in the following figure.

7. OCTAL-TO-BINARY ENCODER

8. OCTAL-TO-BINARY ENCODER

9. Drawbacks of Encoder
There is an ambiguity, when all outputs of encoder are equal to zero.
Because, it could be the code corresponding to the inputs, when only
least significant input is one or when all inputs are zero.
If more than one input is active High, then the encoder produces an
output, which may not be the correct code. For example, if both Y3
and Y6 are „1‟, then the encoder produces 111 at the output. This is
neither equivalent code corresponding to Y3, when it is „1‟ nor the
equivalent code corresponding to Y6, when it is „1‟.

10. Priority Encoder
A 4 to 2 priority encoder has four inputs Y3, Y2, Y1 & Y0
and two outputs A1 & A0. Here, the input, Y3 has the
highest priority, whereas the input, Y0 has the lowest
priority. In this case, even if more than one input is „1‟ at
the same time, the output will be the binary code
corresponding to the input, which is having higher priority.

11. Priority Encoder
• We considered one more output, V in order to know, whether
the code available at outputs is valid or not.
• If at least one input of the encoder is „1‟, then the code
available at outputs is a valid one. In this case, the output, V
will be equal to 1.
• If all the inputs of encoder are „0‟, then the code available at
outputs is not a valid one. In this case, the output, V will be
equal to 0.

12. Priority Encoder
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0 V
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
The Truth table of 4 to 2 priority encoder is shown below.
Use 4 variable K-maps for getting simplified expressions for
each output.

13. Priority Encoder
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0 V
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
The simplified Boolean functions are
A1=Y3+Y2
A0=Y3+Y2′Y1
Similarly, we will get the Boolean function of output, V as
V=Y3+Y2+Y1+Y0

14. Priority Encoder

15. Multiplexer

16. Multiplexer
• It is a combinational circuit which have many data inputs and
single output depending on control or select inputs.​
• For n input lines, log n (base2) selection lines, or we can say
that for 2n input lines, n selection lines are required.
• Since there are „n‟ selection lines, there will be 2n possible
combinations of zeros and ones. So, each combination will
select only one data input. Multiplexer is also called as Mux.

17. 4x1 Multiplexer
• 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two
selection lines s1 & s0 and one output Y. The block diagram of
4x1 Multiplexer is shown in the following figure.

18. 4x1 Multiplexer
Selection Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
From Truth table, we can directly write the
Boolean function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

19. Implementation of Higher-order Multiplexers
• 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer.
• 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output.
• 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
• In first stage, two 4x1 Multiplexers are used to get the 8 data inputs.
• Since, each 4x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as inputs
and to produce the final output.
• Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2,
s1 & s0 and one output Y.

20. Implementation of Higher-order Multiplexers
Selection Inputs Outp
ut
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

21. 16x1 Multiplexer
• Implement 16x1 Multiplexer
using 8x1 Multiplexers and 2x1
Multiplexer.

22. 16x1 Multiplexer

23. Multiplexer with Enable Input
• It's often desirable to add
an enable (or strobe)
input EN to a multiplexer.
• When EN = 0, the output
is 0. When EN = 1, the
multiplexer performs its
operation depending on
the selection line.

25. Boolean Function Implementation using MUX

26. Boolean Function Implementation using MUX

27. Boolean Function Implementation using MUX

28. Boolean Function Implementation using MUX

29. Boolean Function Implementation using MUX

30. Universal Gates
• A universal gate is a gate which can implement any
Boolean function without need to use any other gate type.
• The NAND and NOR gates are universal gates.
• In practice, this is advantageous since NAND and NOR
gates are economical and easier to fabricate and are the
basic gates used in all IC digital logic families.

31. NAND Gate is Universal Gate

32. NAND Gate is Universal Gate

33. NOR Gate is Universal Gate

34. NOR Gate is Universal Gate

35. Exclusive-OR and Equivalence Operation

36. Exclusive-OR and Equivalence Operation

37. Exclusive-OR Operation
Symbol Truth Table
3-input Ex-OR Gate
C B A Q
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Boolean Expression
Q = A ⊕ B ⊕ C
“Any ODD Number of Inputs”
gives Q
An n-variable
exclusive-OR
expression is equal to
the Boolean function
with 2n/2 minterms
whose equivalent
binary numbers have
an odd number of 1‟s.

38. Equivalence Operation
Symbol Truth Table
3-input Ex-OR Gate
C B A Q
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Boolean Expression
Q = A  B  C
“Any EVEN Number of zeroes
in Inputs” gives Q
An n-variable
equivalence
expression is equal to
the Boolean function
with 2n/2 minterms
whose equivalent
binary numbers have
an even number of 0‟s.

39. Exclusive-OR and Equivalence Operation
An n-variable
exclusive-OR
expression is equal to
the Boolean function
with 2n/2 minterms
whose equivalent
binary numbers have
an odd number of 1‟s.

40. Exclusive-OR and Equivalence Operation

41. Exclusive-OR and Equivalence Operation
Truth Table
C B A Q Q‟ T1 T2 T3
0 0 0 0 1 0 1 1
0 0 1 1 0 1 0 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 1
1 0 0 1 0 0 1 0
1 0 1 0 1 1 0 1
1 1 0 0 1 1 0 1
1 1 1 1 0 0 1 0
Q = A xor B xor C
T1 = A xor B
T2 = A xnor B
T3 = T1 xnor C
T4 = T2 xor C

42. Parity Generation
Sender Receiver
Inputs: 3 Outputs: 1
Inputs: X, Y, Z Outputs: p

43. Parity Generation

44. Parity Checker
Sender Receiver
Inputs: 4 Outputs: 1
Inputs: X, Y, Z, P Outputs: C

45. Parity Checker

46. Input: 3 Output: 5
Input: X, Y, Z Output: A, B, C, D, E
X Y Z (XYZ)2 A B C D E F
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 1
0 1 0 4 0 0 0 1 0 0
0 1 1 9 0 0 1 0 0 1
1 0 0 16 0 1 0 0 0 0
1 0 1 25 0 1 1 0 0 1
1 1 0 36 1 0 0 1 0 0
1 1 1 49 1 1 0 0 0 1

47. Input: 3 Output: 5
Input: X, Y, Z Output: A, B, C, D, E
X Y Z A B C D E F
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 1
1 0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1
A
YZ 00 01 11 10
0 0 0 0 0
1 0 0 1 1
B
YZ 00 01 11 10
0 0 0 0 0
1 1 1 0 0
C
YZ 00 01 11 10
0 0 0 1 0
1 0 1 0 0
D
YZ 00 01 11 10
0 0 0 0 1
1 0 0 0 1
E
YZ 00 01 11 10
0 0 0 0 0
1 0 0 0 0
F
YZ 00 01 11 10
0 0 1 1 0
1 0 1 1 0
A = XY B = XY‟ C = X‟YZ + XY‟Z
D = YZ‟ E = 0 F = Z

48. W X Y Z BCD BCD*5 A1 B1 C1 D1 A2 B2 C2 D2
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 5 0 0 0 0 0 1 0 1
0 0 1 0 2 10 0 0 0 1 0 0 0 0
0 0 1 1 3 15 0 0 0 1 0 1 0 1
0 1 0 0 4 20 0 0 1 0 0 0 0 0
0 1 0 1 5 25 0 0 1 0 0 1 0 1
0 1 1 0 6 30 0 0 1 1 0 0 0 0
0 1 1 1 7 35 0 0 1 1 0 1 0 1
1 0 0 0 8 40 0 1 0 0 0 0 0 0
1 0 0 1 9 45 0 1 0 0 0 1 0 1

49. W X Y Z A
1
B
1
C
1
D
1
A
2
B
2
C
2
D
2
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 1 0 0 0 1 0 1 0 1
0 1 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 1 0 0 1 0 1
0 1 1 0 0 0 1 1 0 0 0 0
0 1 1 1 0 0 1 1 0 1 0 1
1 0 0 0 0 1 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 1 0 1
Z
Y
X
W
A2
B2
C2
D2
A1
B1
C1
D1
0
0

51. 8 4 -2 -1
W X Y Z BCD A B C D
0 0 0 0 0 0 0 0 0
0 0 0 1 X X X X X
0 0 1 0 X X X X X
0 0 1 1 X X X X X
0 1 0 0 4 0 1 0 0
0 1 0 1 3 0 0 1 1
0 1 1 0 2 0 0 1 0
0 1 1 1 1 0 0 0 1
1 0 0 0 8 1 0 0 0
1 0 0 1 7 0 1 1 1
1 0 1 0 6 0 1 1 0
1 0 1 1 5 0 1 0 1
1 1 0 0 X X X X X
1 1 0 1 X X X X X
1 1 1 0 X X X X X
1 1 1 1 9 1 0 0 1

52. W X Y Z A B C D
0 0 0 0 0 0 0 0
0 0 0 1 X X X X
0 0 1 0 X X X X
0 0 1 1 X X X X
0 1 0 0 0 1 0 0
0 1 0 1 0 0 1 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 0 1
1 0 0 0 1 0 0 0
1 0 0 1 0 1 1 1
1 0 1 0 0 1 1 0
1 0 1 1 0 1 0 1
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 1 0 0 1
A
YZ 00 01 11 10
00 0 X X X
01 0 0 0 0
11 X X 1 X
10 1 0 0 0
B
YZ 00 01 11 10
00 0 X X X
01 1 0 0 0
11 X X 0 X
10 0 1 1 1
C
YZ 00 01 11 10
00 0 X X X
01 0 1 0 1
11 X X 0 X
10 0 1 0 1
C
YZ 00 01 11 10
00 0 X X X
01 0 1 1 0
11 X X 1 X
10 0 1 1 0
A = WX+WY‟Z‟
B = X‟Y+X‟Z+XY‟Z‟
C = Y‟Z +YZ‟
D = Z

53. 2 4 2 1
W X Y Z A B C D
0 0 0 0 0 0 0 0 0
0 0 0 1 1 0 1 1 1
0 0 1 0 2 0 1 1 0
0 0 1 1 3 0 1 0 1
0 1 0 0 4 0 1 0 0
0 1 0 1 5 1 0 1 1
0 1 1 0 6 1 0 1 0
0 1 1 1 7 1 0 0 1
1 0 0 0 2 0 1 1 0
1 0 0 1 3 0 1 0 1
1 0 1 0 4 0 1 0 0
1 0 1 1 5 1 0 1 1
1 1 0 0 6 1 0 1 0
1 1 0 1 7 1 0 0 1
1 1 1 0 8 1 0 0 0
1 1 1 1 9 1 1 1 1

54. W X Y Z A B C D E
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 0
0 0 1 1 0 0 0 1 1
0 1 0 0 0 0 1 0 0
0 1 0 1 0 0 1 0 1
0 1 1 0 0 0 1 1 0
0 1 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 0 0 1 0 1 0 0 1
1 0 1 0 1 0 0 0 0
1 0 1 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 1 1
1 1 1 0 1 0 1 0 0
1 1 1 1 1 0 1 0 1